可编程逻辑器件开发应用数字电子钟.docx
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可编程逻辑器件开发应用数字电子钟
常州信息职业技术学院
可编程逻辑器件开发应用
综合项目设计报告
2012—2013学年第二学期
项目:
数字电子钟的设计与实现
班级:
学号:
姓名:
授课教师:
制定日期:
2012年06月08日
项目设计报告要求
1、总体设计
(1)分频模块:
可以得到正常的秒信号。
(2)校时模块:
根据当前是否是校时状态,通过按三个键分别对时、分、秒进行校对。
(如:
按校秒键一次,秒加1,按2次,秒加2…)
(3)计时模块:
进行时、分、秒计数处理。
(4)报时模块:
每个整点响几声,(中午12点时未能播放一端音乐)。
数字电子钟的系统功能框图
数码管扫描显示模块
↑
时计数器←分计数器←秒计数器
计时处理模块
↑
↓
报时模块←主控模块←分频模块
↑↑↑
系统清零和暂停/开始正常/校时模式选择校时模块
2、软件设计
分频模块:
得到正常的信号;键盘去抖动。
clk_24MHz:
基本时钟信号输入
sec_narmal:
周期为1S的信号输入
moduledivclk(clk_24MHz,sec_narmal,clk_50Hz);
inputclk_24MHz;
outputsec_narmal,clk_50Hz;
reg[23:
0]count_n;
reg[17:
0]count_50Hz;
regsec_narmal,clk_50Hz;
always@(negedgeclk_24MHz)
begin
count_n=count_n+1;
if(count_n==24'd12000000)
begin
count_n=24'h0;
sec_narmal=~sec_narmal;
end
end
always@(negedgeclk_24MHz)
begin
count_50Hz=count_50Hz+1;
if(count_50Hz==18'd240000)
begin
count_50Hz=18'h0;
clk_50Hz=~clk_50Hz;
end
end
endmodule
校时模块:
keysel:
校时状态/正常计时状态选择键输入
key_s:
校秒信号选择键输入
key_m:
校分信号选择键输入
key_h:
校时信号选择输入
sec_narmal:
周期为1S的信号输入
进入校时状态,通过按三个键分别对时、分、秒进行校对。
按键每按一次、加1.
modulemodify(clk_50Hz,keysel,key_s,key_m,key_h,min2);
inputclk_50Hz;
inputkeysel;
inputkey_s,key_m,key_h;
output[23:
0]min2;
regkey1,key2,key3;
reg[23:
0]min_2;
always@(negedgeclk_50Hz)
begin
if(!
keysel)
begin
key1=key_s;
key2=key_m;
key3=key_h;
end
end
always@(negedgekey1)
begin
min_2[3:
0]=min_2[3:
0]+1;/秒的校时/
if(min_2[3:
0]==4'ha)
begin
min_2[3:
0]=4'h0;/秒的个位0-9/
min_2[7:
4]=min2[7:
4]+1;/秒的十位0-6/
if(min_2[7:
4]==4'h6)min_2[7:
4]=4'h0;
end
end
always@(negedgekey2)
begin
min_2[11:
8]=min_2[11:
8]+1;
if(min_2[11:
8]==4'ha)
begin
min_2[11:
8]=4'h0;/分的个位0-9/
min_2[15:
12]=min_2[15:
12]+1;;/分的十位0-6/
if(min_2[15:
12]==4'h6)min_2[15:
12]=4'h0;
end
end
always@(negedgekey3)
begin
min_2[19:
16]=min_2[19:
16]+1;
if(min_2[19:
16]==4'ha)
begin
min_2[19:
16]=4'h0;
min_2[23:
20]=min_2[23:
20]+1;
end
if(min_2[23:
16]==8'h24)min_2[23:
16]=8'h0;
end
assignmin2=min_2;
endmodule
计时处理模块:
sec:
计时信号输入
keyclr:
计时清零键
keyen:
计时开始键
min:
计时结果输出
当按下keyen键时、开始正常走时、
modulecounttime(sec,keysel,keyclr,keyen,min1,min_1);
inputsec;
inputkeyclr,keyen,keysel;
input[23:
0]min1;
output[23:
0]min_1;
reg[23:
0]min,min_1;
always
begin
if(!
keysel)min_1=min1;
elsemin_1=min;
end
always@(posedgesec)
begin
if(!
keysel)min=min1;
else
begin
if(!
keyclr)min=24'h0;
else
if(!
keyen)
begin
min=min+1;
if(min[3:
0]==4'ha)
begin
min[3:
0]=4'h0;
min[7:
4]=min[7:
4]+1;
if(min[7:
4]==4'h6)
begin
min[7:
4]=4'h0;
min[11:
8]=min[11:
8]+1;
if(min[11:
8]==4'ha)
begin
min[11:
8]=4'h0;
min[15:
12]=min[15:
12]+1;
if(min[15:
12]==4'h6)
begin
min[15:
12]=4'h0;
min[19:
16]=min[19:
16]+1;
if(min[19:
16]==4'ha)
begin
min[19:
16]=4'h0;
min[23:
20]=min[23:
20]+1;
end
if(min[23:
16]==8'h24)min[23:
16]=0;
end
end
end
end
end
end
end
endmodule
报时模块:
min:
基本时钟信号输入
buzzout:
声响输出
modulemusic(clk,min,buzzout);
inputclk;
input[23:
0]min;
outputbuzzout;
reg[3:
0]high,med,low;
regbuzzout_reg;
reg[24:
0]count1,count2;
reg[20:
0]count_end;
reg[7:
0]counter;
regclk_4Hz;
always@(posedgeclk)
begin
if(count1<22'd3000000)
begin
count1=count1+1;
end
else
begin
count1=0;
clk_4Hz=~clk_4Hz;
end
end
always@(posedgeclk)
begin
count2=count2+1;
if((min[15:
0]>=16'h5945)&&(min[15:
0]<=16'h5959))
begin
if((count2==count_end)&&(min[23:
16]==8'h11))
begin
buzzout_reg=!
buzzout_reg;
count2=25'h0;
end
elseif(min[23:
16]!
=8'h11)
begin
buzzout_reg=!
(count2[10]&count2[18]&count2[23]);
end
end
end
always@(posedgeclk_4Hz)
begin
case({high,med,low})
9'b000000001:
count_end=16'hbb9a;
9'b000000010:
count_end=16'ha72f;
9'b000000011:
count_end=16'h94f2;
9'b000000100:
count_end=16'h8e78;
9'b000000101:
count_end=16'h7d63;
9'b000000110:
count_end=16'h6fb5;
9'b000000111:
count_end=16'h637f;
9'b000001000:
count_end=16'h5dfb;
9'b000010000:
count_end=16'h53bb;
9'b000011000:
count_end=16'h4a95;
9'b000100000:
count_end=16'h4651;
9'b000101000:
count_end=16'h3eb1;
9'b000110000:
count_end=16'h37da;
9'b000111000:
count_end=16'h31bf;
9'b001000000:
count_end=16'h2ef2;
9'b010000000:
count_end=16'h29d4;
9'b011000000:
count_end=16'h2543;
9'b100000000:
count_end=16'h232f;
9'b101000000:
count_end=16'h1f58;
9'b110000000:
count_end=16'h1bed;
9'b111000000:
count_end=16'h18df;
default:
count_end=16'hffff;
endcase
end
always@(posedgeclk_4Hz)
begin
if(counter==47)
counter=0;
else
counter=counter+1;
case(counter)
0:
{high,med,low}=9'b000000011;
1:
{high,med,low}=9'b000000011;
2:
{high,med,low}=9'b000000011;
3:
{high,med,low}=9'b000000011;
4:
{high,med,low}=9'b000000101;
5:
{high,med,low}=9'b000000101;
6:
{high,med,low}=9'b000000101;
7:
{high,med,low}=9'b000000110;
8:
{high,med,low}=9'b000001000;
9:
{high,med,low}=9'b000001000;
10:
{high,med,low}=9'b000001000;
11:
{high,med,low}=9'b000010000;
12:
{high,med,low}=9'b000000110;
13:
{high,med,low}=9'b000001000;
14:
{high,med,low}=9'b000000101;
15:
{high,med,low}=9'b000000101;
16:
{high,med,low}=9'b000101000;
17:
{high,med,low}=9'b000101000;
18:
{high,med,low}=9'b000101000;
19:
{high,med,low}=9'b001000000;
20:
{high,med,low}=9'b000110000;
21:
{high,med,low}=9'b000101000;
22:
{high,med,low}=9'b000011000;
23:
{high,med,low}=9'b000101000;
24:
{high,med,low}=9'b000010000;
25:
{high,med,low}=9'b000010000;
26:
{high,med,low}=9'b000010000;
27:
{high,med,low}=9'b000010000;
28:
{high,med,low}=9'b000010000;
29:
{high,med,low}=9'b000010000;
30:
{high,med,low}=9'b000010000;
31:
{high,med,low}=9'b000010000;
32:
{high,med,low}=9'b000010000;
33:
{high,med,low}=9'b000010000;
34:
{high,med,low}=9'b000010000;
35:
{high,med,low}=9'b000011000;
36:
{high,med,low}=9'b000000111;
37:
{high,med,low}=9'b000000111;
38:
{high,med,low}=9'b000000110;
39:
{high,med,low}=9'b000000110;
40:
{high,med,low}=9'b000000101;
41:
{high,med,low}=9'b000000101;
42:
{high,med,low}=9'b000000101;
43:
{high,med,low}=9'b000000110;
44:
{high,med,low}=9'b000001000;
45:
{high,med,low}=9'b000001000;
46:
{high,med,low}=9'b000010000;
47:
{high,med,low}=9'b000010000;
endcase
end
assignbuzzout=buzzout_reg;
endmodule
显示模块:
sled_reg:
数码管段码输出
sl_reg:
数码管位码输出
seg_reg:
单个数码管输出
moduledisplay(keysel,clk_24MHz,sec,min,sled_reg,sl_reg,seg_reg);
inputclk_24MHz;
inputsec,keysel;
input[23:
0]min;
output[7:
0]sled_reg,seg_reg;
output[3:
0]sl_reg;
reg[3:
0]sl_reg;
reg[7:
0]sled_reg,seg_reg;
reg[15:
0]count;
reg[3:
0]ledbuf;
always@(negedgeclk_24MHz)
begin
count=count+1;
end
always@(count[11:
10])
begin
case(count[11:
10])
2'h0:
ledbuf=min[3:
0];
2'h1:
ledbuf=min[7:
4];
2'h2:
ledbuf=min[11:
8];
2'h3:
ledbuf=min[15:
12];
endcase
case(count[11:
10])
2'h0:
sl_reg=4'b0111;
2'h1:
sl_reg=4'b1011;
2'h2:
sl_reg=4'b1101;
2'h3:
sl_reg=4'b1110;
endcase
end
always@(ledbuf)
begin
case(ledbuf)
4'h0:
sled_reg=8'hc0;
4'h1:
sled_reg=8'hf9;
4'h2:
sled_reg=8'ha4;
4'h3:
sled_reg=8'hb0;
4'h4:
sled_reg=8'h99;
4'h5:
sled_reg=8'h92;
4'h6:
sled_reg=8'h82;
4'h7:
sled_reg=8'hf8;
4'h8:
sled_reg=8'h80;
4'h9:
sled_reg=8'h90;
4'ha:
sled_reg=8'h88;
4'hb:
sled_reg=8'h83;
4'hc:
sled_reg=8'hc6;
4'hd:
sled_reg=8'ha1;
4'he:
sled_reg=8'h86;
4'hf:
sled_reg=8'h8e;
endcase
if((count[11:
10]==2'b10)&sec)sled_reg=sled_reg&8'h7f;
end
always@(min[23:
16])
begin
case(min[23:
16])
8'h0:
seg_reg=8'h3f;
8'h1:
seg_reg=8'h06;
8'h2:
seg_reg=8'h5b;
8'h3:
seg_reg=8'h4f;
8'h4:
seg_reg=8'h66;
8'h5:
seg_reg=8'h6d;
8'h6:
seg_reg=8'h7d;
8'h7:
seg_reg=8'h07;
8'h8:
seg_reg=8'h7f;
8'h9:
seg_reg=8'h6f;
8'h10:
seg_reg=8'h77;
8'h11:
seg_reg=8'h7c;
8'h12:
seg_reg=8'hbf;
8'h13:
seg_reg=8'h86;
8'h14:
seg_reg=8'hdb;
8'h15:
seg_reg=8'hcf;
8'h16:
seg_reg=8'he6;
8'h17:
seg_reg=8'hed;
8'h18:
seg_reg=8'hfd;
8'h19:
seg_reg=8'h87;
8'h20:
seg_reg=8'hff;
8'h21:
seg_reg=8'hef;
8'h22:
seg_reg=8'hf7;
8'h23:
seg_reg=8'hfc;
endcase
end
endmodule
顶层模块:
moduletime_count(clk_24MHz,keysel,key_s,key_m,key_h,keyclr,keyen,sled_reg,sl_reg,seg_reg,buzzout);
inputclk_24MHz;
inputkeyclr,keyen,keysel;
inputkey_s,key_m,key_h;
outputbuzzout;
output[7:
0]sled_reg,seg_reg;
output[3:
0]sl_reg;
wiresec,clk_50Hz;
wire[23:
0]min,min2;
divclkQ1(clk_24MHz,sec,clk_50Hz);
modifyQ2(clk_50Hz,keysel,key_s,key_m,key_h,min2);
counttimeQ3(sec,keysel,keyclr,keyen,min2,min);
displayQ4(keysel,clk_24MHz,sec,min,sled_reg,sl_reg,seg_reg);
musicQ5(sec,clk_24MHz,min,buzzout);
endmodule
3、程序测试
(一)调试方法
(1)、双击QuartusⅡ软件快捷图标进入QuartusⅡ集成开发环境,新建工程项目文件clock.qpf,并在该项目下分别新建Verilog源文件clock.v、divclk.v、modify.v、countetime.v、music.v和display.v这6个文件,输入上面的程序代码并保存。
(2)、为该工程项目选择一个目标器件,并对相应的引脚进行锁定,在些所选择的器件应该是Altera公司的EPM1270T144C5N芯片,引脚锁定方法如表所示:
引脚号
引脚名
引脚号
引脚名
118
Seld0
124
Seg0
117
Seld1
123
Seg1
114
Seld2
121
Seg2
113
Seld3
120
Seg3
112
Seld4
119
Seg4
111
Seld5
125
Seg5
110
Seld6
127
Seg6
109
Seld7
122
Seg7
108
Sl0
61
Keyclr
107
Sl1
71
Keyen
106
Sl2
18
Clk
105
Sl3
(3)、对该工程文件进行编译处理,若在编译过程中发现错误,则需找出并更正错误,直至成功为止。
将CCITCPLD/FPGAJTAG下载电缆的两端分别接到PC机和CCITCPLD/FPGA实验仪上,在打开电源,执行下载命令把程序下载到CCIT