SIGNAL INTEGRITY信号完整性 外文翻译.docx

SIGNAL INTEGRITY信号完整性 外文翻译.docx

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SIGNALINTEGRITY信号完整性外文翻译

SIGNALINTEGRITY

RaymondY.Chen,Sigrid,Inc.,SantaClara,California

Introduction

Intherealmofhigh-speeddigitaldesign,signalintegrityhasbecomeacriticalissue,andisposingincreasingchallengestothedesignengineers.ManysignalintegrityproblemsareelectromagneticphenomenainnatureandhencerelatedtotheEMI/EMCdiscussionsintheprevioussectionsofthisbook.Inthischapter,wewilldiscusswhatthetypicalsignalintegrityproblemsare,wheretheycomefrom,whyitisimportanttounderstandthemandhowwecananalyzeandsolvetheseissues.Severalsoftwaretoolsavailableatpresentforsignalintegrityanalysisandcurrenttrendsinthisareawillalsobeintroduced.

ThetermSignalIntegrity（SI）addressestwoconcernsintheelectricaldesignaspects–thetimingandthequalityofthesignal.Doesthesignalreachitsdestinationwhenitissupposedto?

Andalso,whenitgetsthere,isitingoodcondition?

Thegoalofsignalintegrityanalysisistoensurereliablehigh-speeddatatransmission.Inadigitalsystem,asignalistransmittedfromonecomponenttoanotherintheformoflogic1or0,whichisactuallyatcertainreferencevoltagelevels.Attheinputgateofareceiver,voltageabovethereferencevalueVihisconsideredaslogichigh,whilevoltagebelowthereferencevalueVilisconsideredaslogiclow.Figure14-1showstheidealvoltagewaveformintheperfectlogicworld,whereasFigure14-2showshowsignalwilllooklikeinarealsystem.Morecomplexdata,composedofastringofbit1and0s,areactuallycontinuousvoltagewaveforms.Thereceivingcomponentneedstosamplethewaveforminordertoobtainthebinaryencodedinformation.ThedatasamplingprocessisusuallytriggeredbytherisingedgeorthefallingedgeofaclocksignalasshownintheFigure14-3.Itisclearfromthediagramthatthedatamustarriveatthereceivinggateontimeandsettledowntoanon-ambiguouslogicstatewhenthereceivingcomponentstartstolatchin.Anydelayofthedataordistortionofthedatawaveformwillresultinafailureofthedatatransmission.ImagineifthesignalwaveforminFigure14-2exhibitsexcessiveringingintothelogicgrayzonewhilethesamplingoccurs,thenthelogiclevelcannotbereliablydetected.

SIProblems

TypicalSIProblems

“Timing”iseverythinginahigh-speedsystem.Signaltimingdependsonthedelaycausedbythephysicallengththatthesignalmustpropagate.Italsodependsontheshapeofthewaveformwhenthethresholdisreached.Signalwaveformdistortionscanbecausedbydifferentmechanisms.Buttherearethreemostlyconcernednoiseproblems:

•ReflectionNoiseDuetoimpedancemismatch,stubs,visaandotherinterconnectdiscontinuities.

•CrosstalkNoiseDuetoelectromagneticcouplingbetweensignaltracesandvisa.

•Power/GroundNoiseDuetoparasiticofthepower/grounddeliverysystemduringdrivers’simultaneousswitchingoutput（SSO）.ItissometimesalsocalledGroundBounce,Delta-INoiseorSimultaneousSwitchingNoise（SSN）.

BesidesthesethreekindsofSIproblems,thereisotherElectromagneticCompatibilityorElectromagneticInterference（EMC/EMI）problemsthatmaycontributetothesignalwaveformdistortions.WhenSIproblemshappenandthesystemnoisemarginrequirementsarenotsatisfied–theinputtoaswitchingreceivermakesaninflectionbelowVihminimumoraboveVilmaximum;theinputtoaquietreceiverrisesaboveVilmaximumorfallsbelowVihminimum;power/groundvoltagefluctuationsdisturbthedatainthelatch,thenlogicerror,datadrop,falseswitching,orevensystemfailuremayoccur.Thesetypesofnoisefaultsareextremelydifficulttodiagnoseandsolveafterthesystemisbuiltorprototyped.Understandingandsolvingtheseproblemsbeforetheyoccurwilleliminatehavingtodealwiththemfurtherintotheprojectcycle,andwillinturncutdownthedevelopmentcycleandreducethecost[1].Inthelaterpartofthischapter,wewillhavefurtherinvestigationsonthephysicalbehaviorofthesenoisephenomena,theircauses,theirelectricalmodelsforanalysisandsimulation,andthewaystoavoidthem.

1.WhereSIProblemsHappen

Sincethesignalstravelthroughallkindsofinterconnectionsinsideasystem,anyelectricalimpacthappeningatthesourceend,alongthepath,oratthereceivingend,willhavegreateffectsonthesignaltimingandquality.Inatypicaldigitalsystemenvironment,signalsoriginatingfromtheoff-chipdriversonthedie（thechip）gothroughc4orwire-bondconnectionstothechippackage.Thechippackagecouldbesinglechipcarrierormulti-chipmodule（MCM）.Throughthesolderbumpsofthechippackage,signalsgotothePrintedCircuitBoard（PCB）level.Atthislevel,typicalpackagingstructuresincludedaughtercard,motherboardorbackplane.Thensignalscontinuetogotoanothersystemcomponent,suchasanASIC（ApplicationSpecificIntegratedCircuit）chip,amemorymoduleoraterminationblock.Thechippackages,printedcircuitboards,aswellasthecablesandconnecters,formtheso-calleddifferentlevelsofelectronicpackagingsystems,asillustratedinFigure14-4.Ineachlevelofthepackagingstructure,therearetypicalinterconnects,suchasmetaltraces,visa,andpower/groundplanes,whichformelectricalpathstoconductthesignals.Itisthepackaginginterconnectionthatultimatelyinfluencesthesignalintegrityofasystem.

2.SIInElectronicPackaging

Technologytrendstowardhigherspeedandhigherdensitydeviceshavepushedthepackageperformancetoitslimits.Theclockrateofpresentpersonalcomputersisapproachinggigahertzrange.Assignalrise-timebecomeslessthan200ps,thesignificantfrequencycontentofdigitalsignalsextendsuptoatleast10GHz.Thisnecessitatesthefabricationofinterconnectsandpackagestobecapableofsupportingveryfastvaryingandbroadbandsignalswithoutdegradingsignalintegritytounacceptablelevels.Whilethechipdesignandfabricationtechnologyhaveundergoneatremendousevolution:

gatelengths,havingscaledfrom50µminthe1960sto0.18µmtoday,areprojectedtoreach0.1µminthenextfewyears;on-chipclockfrequencyisdoublingevery18months;andtheintrinsicdelayofthegateisdecreasingexponentiallywithtimetoafewtensofPico-seconds.However,thepackagedesignhaslaggedconsiderably.Withcurrenttechnology,thepackageinterconnectiondelaydominatesthesystemtimingbudgetandbecomes

thebottleneckofthehigh-speedsystemdesign.Itisgenerallyacceptedtodaythatpackageperformanceisoneofthemajorlimitingfactorsoftheoverallsystemperformance.

Advancesinhighperformancesub-micronmicroprocessors,thearrivalofgigabitnetworks,andtheneedforbroadbandInternetaccess,necessitatethedevelopmentofhighperformancepackagingstructuresforreliablehigh-speeddatatransmissioninsideeveryelectronicssystem.Signalintegrityisoneofthemostimportantfactorstobeconsideredwhendesigningthesepackages（chipcarriersandPCBs）andintegratingthesepackagestogether.

3、SIAnalysis

3.1.SIAnalysisintheDesignFlow

Signalintegrityisnotanewphenomenonanditdidnotalwaysmatterintheearlydaysofthedigitalera.ButwiththeexplosionoftheinformationtechnologyandthearrivalofInternetage,peopleneedtobeconnectedallthetimethroughvarioushigh-speeddigitalcommunication/computingsystems.Inthisenormousmarket,signalintegrityanalysiswillplayamoreandmorecriticalroletoguaranteethereliablesystemoperationoftheseelectronicsproducts.Withoutpre-layoutSIguidelines,prototypesmayneverleavethebench;withoutpost-layoutSIverifications,productsmayfailinthefield.Figure14-5showstheroleofSIanalysisinthehigh-speeddesignprocess.Fromthischart,wewillnoticethatSIanalysisisappliedthroughoutthedesignflowandtightlyintegratedintoeachdesignstage.ItisalsoverycommontocategorizeSIanalysisintotwomainstages:

rerouteanalysisandpostrouteanalysis.

Inthereroutestage,SIanalysiscanbeusedtoselecttechnologyforI/Os,clockdistributions,chippackagetypes,componenttypes,boardstickups,pinassignments,nettopologies,andterminationstrategies.Withvariousdesignparametersconsidered,batchSIsimulationsondifferentcornercaseswillprogressivelyformulateasetofoptimizedguidelinesforphysicaldesignsoflaterstage.SIanalysisatthisstageisalsocalledconstraintdrivenSIdesignbecausetheguidelinesdevelopedwillbeusedasconstraintsforcomponentplacementandrouting.TheobjectiveofconstraintdrivenSIdesignatthereroutestageistoensurethatthesignalintegrityofthephysicallayout,whichfollowstheplacement/routingconstraintsfornoiseandtimingbudget,willnotexceedthemaximumallowablenoiselevels.Comprehensiveandin-depthrerouteSIanalysiswillcutdowntheredesigneffortsandplace/routeiterations,andeventuallyreducedesigncycle.

Withaninitialphysicallayout,postrouteSIanalysisverifiesthecorrectnessoftheSIdesignguidelinesandconstraints.ItchecksSIviolationsinthecurrentdesign,suchasreflectionnoise,ringing,crosstalkandgroundbounce.ItmayalsouncoverSIproblemsthatareoverlookedinthereroutestage,becausepostrouteanalysisworkswithphysicallayoutdataratherthanestimateddataormodels,thereforeitshouldproducemoreaccuratesimulationresults.

WhenSIanalysisisthoroughlyimplementedthroughoutthewholedesignprocess,areliablehighperformancesystemcanbeachievedwithfastturn-around.

Inthepast,physicaldesignsgeneratedbylayoutengineersweremerelymechanicaldrawingswhenverylittleornosi