jishu_1ms<=jishu_1ms+1'b1;
else
jishu_1ms<=16'b0;
end
assignen_1s=(jishu_1s==cnt_1s)?
1'b1:
1'b0;//1s
assignen_1ms=(jishu_1ms==cnt_1ms)?
1'b1:
1'b0;//1ms
endmodule
//按键控制部分
moduleanjian(clk,rst_n,key1,key2,key1_low,key2_low);
inputclk;
inputrst_n;
inputkey1;//分加
inputkey2;//分减
outputkey1_low;//按键按下消抖后的标志位
outputkey2_low;
regreg0_key;//key1消抖
regreg1_key;
regreg2_key;//key2消抖
regreg3_key;
always@(posedgeclkornegedgerst_n)
begin
if(!
rst_n)
begin
reg0_key<=1'b1;
reg1_key<=1'b1;
end
else
begin
reg0_key<=key1;
reg1_key<=reg0_key;//根据非阻塞赋值的原理,reg1_key存储的值是reg0_key上一个时钟的值
end
end
//脉冲边沿检测法,当寄存器key1由1变为0时,key1_an的值变为高,维持一个时钟周期
wirekey1_an;
assignkey1_an=reg1_key&(~reg0_key);
always@(posedgeclkornegedgerst_n)
begin
if(!
rst_n)
begin
reg2_key<=1'b1;
reg3_key<=1'b1;
end
else
begin
reg2_key<=key2;
reg3_key<=reg2_key;
end
end
//脉冲边沿检测法,当寄存器key2由1变为0时,key2_an的值变为高,维持一个时钟周期
wirekey2_an;
assignkey2_an=reg3_key&(~reg2_key);
reg[19:
0]cnt_key1;//计数寄存器
always@(posedgeclkornegedgerst_n)
begin
if(!
rst_n)
cnt_key1<=20'd0;//异步复位
elseif(key1_an)
cnt_key1<=20'd0;//led1_an=1,按键确认按下,cnt_key1从0开始计数
else
cnt_key1<=cnt_key1+1'b1;
end
reg[19:
0]cnt_key2;//计数寄存器
always@(posedgeclkornegedgerst_n)
begin
if(!
rst_n)
cnt_key2<=20'd0;
elseif(key2_an)
cnt_key2<=20'd0;
else
cnt_key2<=cnt_key2+1'b1;
end
//以下为消抖程序
regreg_low;
regreg1_low;
always@(posedgeclkornegedgerst_n)
begin
if(!
rst_n)
begin
reg_low<=1'b1;
end
elseif(cnt_key1==20'hfffff)//时钟50mhz的话大约计时是20ms
begin
reg_low<=key1;//led_an=1,按键确认按下,cnt_key从0开始计数,这时候还有消抖动,计数20ms后抖动滤除了此时再锁存一下key1的值
end//这时key1的值就稳定了
end
always@(posedgeclkornegedgerst_n)
begin
if(!
rst_n)
reg1_low<=1'b1;
else
reg1_low<=reg_low;
end
assignkey1_low=reg1_low&(~reg_low);//当寄存器reg_low由1变为0时,key_low的值变为高,维持一个时钟周期
regreg2_low;
regreg3_low;
always@(posedgeclkornegedgerst_n)
begin
if(!
rst_n)
begin
reg2_low<=1'b1;
end
elseif(cnt_key2==20'hfffff)
begin
reg2_low<=key2;
end
end
always@(posedgeclkornegedgerst_n)
begin
if(!
rst_n)
reg3_low<=1'b1;
else
reg3_low<=reg2_low;
end
assignkey2_low=reg3_low&(~reg2_low);
endmodule
//时、分、秒
moduleshijian(clk,rst_n,en_1s,key1_low,key2_low,shi,fen,miao);
inputclk;
inputrst_n;
inputen_1s;
inputkey1_low;
inputkey2_low;
output[5:
0]shi;
output[5:
0]fen;
output[5:
0]miao;
reg[5:
0]shi;
reg[5:
0]fen;
reg[5:
0]miao;
always@(posedgeclkornegedgerst_n)
begin
if(!
rst_n)
begin
shi<=6'b0;
fen<=6'b0;
miao<=6'b0;
end
elseif(en_1s)
begin
miao=miao+1'b1;
if(miao==60)
begin
miao=0;
fen=fen+1'b1;
if(fen==60)
begin
fen=0;
shi=shi+1'b1;
if(shi==24)
shi=0;
end
end
end
elseif(key1_low)
begin
fen=fen+1'b1;
if(fen==60)
begin
fen=0;
shi=shi+1'b1;
if(shi==24)
shi=0;
end
end
elseif(key2_low)
begin
fen=fen-1'b1;
if(fen==0)
begin
shi=shi-1'b1;
fen=59;
end
end
else
begin
shi<=shi;
fen<=fen;
miao<=miao;
end
end
endmodule
//显示部分
modulexianshi(clk,rst_n,en_1ms,shi,fen,miao,led_bit,dataout);
inputclk;
inputrst_n;
inputen_1ms;
input[5:
0]shi;
input[5:
0]fen;
input[5:
0]miao;
output[7:
0]led_bit;//位选
output[7:
0]dataout;//段选
//数码管显示0~9对应段选输出
parameternum0=8'b11000000,
num1=8'b11111001,
num2=8'b10100100,
num3=8'b10110000,
num4=8'b10011001,
num5=8'b10010010,
num6=8'b10000010,
num7=8'b11111000,
num8=8'b10000000,
num9=8'b10010000;
reg[3:
0]shi1,shi2,fen1,fen2,miao1,miao2;
reg[7:
0]led_bit;//位选
reg[7:
0]dataout;//段选
reg[2:
0]state;//状态寄存器
always@(posedgeclkornegedgerst_n)
if(!
rst_n)
begin
led_bit<=8'b1;
state<=3'b0;
end
elseif(en_1ms)
begin
state<=state+1'b1;
shi1=shi/10;
shi2=shi%10;
fen1=fen/10;
fen2=fen%10;
miao1=miao/10;
miao2=miao%10;
if(state==3'b000)
begin
led_bit=8'b11111110;
case(miao2)
0:
dataout<=num0;
1:
dataout<=num1;
2:
dataout<=num2;
3:
dataout<=num3;
4:
dataout<=num4;
5:
dataout<=num5;
6:
dataout<=num6;
7:
dataout<=num7;
8:
dataout<=num8;
9:
dataout<=num9;
default:
dataout<=num0;
endcase
end
elseif(state==3'b001)
begin
led_bit=8'b11111101;
case(miao1)
0:
dataout<=num0;
1:
dataout<=num1;
2:
dataout<=num2;
3:
dataout<=num3;
4:
dataout<=num4;
5:
dataout<=num5;
default:
dataout<=num0;
endcase
end
elseif(state==3'b010)
begin
led_bit=8'b11110111;
case(fen2)
0:
dataout<=num0;
1:
dataout<=num1;
2:
dataout<=num2;
3:
dataout<=num3;
4:
dataout<=num4;
5:
dataout<=num5;
6:
dataout<=num6;
7:
dataout<=num7;
8:
dataout<=num8;
9:
dataout<=num9;
default:
dataout<=num0;
endcase
end
elseif(state==3'b011)
begin
led_bit=8'b11101111;
case(fen1)
0:
dataout<=num0;
1:
dataout<=num1;
2:
dataout<=num2;
3:
dataout<=num3;
4:
dataout<=num4;
5:
dataout<=num5;
endcase
end
elseif(state==3'b100)
begin
led_bit=8'b10111111;
case(shi2)
0:
dataout<=num0;
1:
dataout<=num1;
2:
dataout<=num2;
3:
dataout<=num3;
4:
dataout<=num4;
default:
dataout<=num0;
endcase
end
elseif(state==3'b101)
begin
led_bit=8'b01111111;
case(shi1)
0:
dataout<=num0;
1:
dataout<=num1;
2:
dataout<=num2;
endcase
end
elseif(state==3'b110)
begin
led_bit=8'b11011011;
dataout<=8'b10111111;
end
end
else
begin
dataout<=dataout;
led_bit<=led_bit;
end
endmodule
//顶层模块
moduleShizhong(clk,rst_n,key1,key2,led_bit,dataout);
inputclk;
inputrst_n;
inputkey1;
inputkey2;
output[7:
0]led_bit;
output[7:
0]dataout;
wireen_1s;
wireen_1ms;
wire[5:
0]shi;
wire[5:
0]fen;
wire[5:
0]miao;
wirekey1_low,key2_low;
fenpinfenpin_int(.clk(clk),
.rst_n(rst_n),
.en_1s(en_1s),
.en_1ms(en_1ms)
);
anjiananjian_int(.clk(clk),
.rst_n(rst_n),
.key1(key1),
.key2(key2),
.key1_low(key1_low),
.key2_low(key2_low)
);
shijianshijian_int(.clk(clk),
.rst_n(rst_n),
.en_1s(en_1s),
.key1_low(key1_low),
.key2_low(key2_low),
.shi(shi),
.fen(fen),
.miao(miao)
);
xianshixianshi_int(.clk(clk),
.rst_n(rst_n),
.en_1ms(en_1ms),
.shi(shi),
.fen(fen),
.miao(miao),
.led_bit(led_bit),
.dataout(dataout)
);
endmodule