VHDL实例演示程序.docx
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VHDL实例演示程序
一、组合逻辑电路的设计实例
●与非门
●加法器
●编码器
●译码器
●数据选择器
●练习题:
2输入异或门、数据分配器
1.三输入“与非”门电路
1)数据流描述
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYnand3IS
PORT(a,b,c:
INBIT;
y:
OUTBIT);
ENDnand3;
ARCHITECTURErtlOFnand3IS
BEGIN
y<=NOT(aANDbANDc);
ENDrtl;
2)行为描述
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYnand3IS
PORT(a,b,c:
INBIT;
y:
OUTBIT);
ENDnand3;
ARCHITECTUREbehaveOFnand3IS
BEGIN
PROCESS(a,b,c)
BEGIN
IF(a='1'ANDb='1'ANDc='1')THEN
y<='0';
ELSE
y<='1';
ENDIF;
ENDPROCESS;
ENDbehave;
3)真值表
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYnand3IS
PORT(a,b,c:
INBIT;
y:
OUTBIT);
ENDnand3;
ARCHITECTUREbehave2OFnand3IS
BEGIN
PROCESS(a,b,c)
VARIABLEtmp:
BIT_VECTOR(2DOWNTO0);
BEGIN
tmp:
=a&b&c;
CASEtmpIS
WHEN"000"=>y<='1';
WHEN"001"=>y<='1';
WHEN"010"=>y<='1';
WHEN"011"=>y<='1';
WHEN"100"=>y<='1';
WHEN"101"=>y<='1';
WHEN"110"=>y<='1';
WHEN"111"=>y<='0';
ENDCASE;
ENDPROCESS;
ENDbehave2;
4)结构描述方式
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYnand3IS
PORT(a,b,c:
INBIT;
y:
OUTBIT);
ENDnand3;
ARCHITECTUREstructureOFnand3IS
SIGNALtemp:
BIT;
COMPONENTand3IS
PORT(a1,b1,c1:
INBIT;
y1:
OUTBIT);
ENDCOMPONENT;
COMPONENTinvIS
PORT(a2:
INBIT;
y2:
OUTBIT);
ENDCOMPONENT;
BEGIN
u1:
and3PORTMAP(a,b,c,temp);
u2:
invPORTMAP(temp,y);
ENDstructure;
2.加法器
见第三章描述方式:
三种描述方式描述全加器。
3.优先编码器
8线-3线优先编码器:
若8输入中的一个输入有效(低电平有效),则此输入对应的3位二进制编码输出;若多个输入有效,则输出优先级高的输入对应的编码。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYpriorityencoderIS
PORT(i:
INSTD_LOGIC_VECTOR(7DOWNTO0);
y:
OUTSTD_LOGIC_VECTOR(2DOWNTO0));
ENDpriorityencoder;
ARCHITECTUREarchiOFpriorityencoderIS
BEGIN
PROCESS(i)
BEGIN
IF(i(0)='0')THEN
y<="111";
ELSIF(i
(1)='0')THEN
y<="110";
ELSIF(i
(2)='0')THEN
y<="101";
ELSIF(i(3)='0')THEN
y<="100";
ELSIF(i(4)='0')THEN
y<="011";
ELSIF(i(5)='0')THEN
y<="010";
ELSIF(i(6)='0')THEN
y<="001";
ELSIF(i(7)='0')THEN
y<="000";
ENDIF;
ENDPROCESS;
ENDarchi;
4.LED七段数码管显示译码器
把二进制代码翻译为十进制,并在数码管上显示出来。
译码器:
4个输入a3,a2,a1,a0:
用来表示0000-1001,即十进制的0-9;
7个输出a,b,c,d,e,f,g:
用来驱动七段可发光的二极管,假设逻辑1用来点亮二极管,逻辑0用来熄灭二极管。
1)选择信号赋值语句
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYymqIS
PORT(a3,a2,a1,a0:
INSTD_LOGIC;
a,b,c,d,e,f,g:
OUTSTD_LOGIC);
ENDymq;
ARCHITECTUREaa1OFymqIS
SIGNALnum:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALdout_temp:
STD_LOGIC_VECTOR(6DOWNTO0);
BEGIN
num<=a3&a2&a1&a0;
WITHnumSELECT
dout_temp<="1111110"WHEN"0000",
"0110000"WHEN"0001",
"1101101"WHEN"0010",
"1111001"WHEN"0011",
"0110011"WHEN"0100",
"1011011"WHEN"0101",
"1011111"WHEN"0110",
"1110000"WHEN"0111",
"1111111"WHEN"1000",
"1111011"WHEN"1001",
"1001111"WHENOTHERS;
a<=dout_temp(6);
b<=dout_temp(5);
c<=dout_temp(4);
d<=dout_temp(3);
e<=dout_temp
(2);
f<=dout_temp
(1);
g<=dout_temp(0);
ENDaa1;
2)CASE语句
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYymqIS
PORT(a3,a2,a1,a0:
INSTD_LOGIC;
a,b,c,d,e,f,g:
OUTSTD_LOGIC);
ENDymq;
ARCHITECTUREaa2OFymqIS
SIGNALdout_temp:
STD_LOGIC_VECTOR(6DOWNTO0);
BEGIN
PROCESS(a3,a2,a1,a0)
VARIABLEnum:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
num:
=a3&a2&a1&a0;
CASEnumIS
WHEN"0000"=>dout_temp<="1111110";
WHEN"0001"=>dout_temp<="0110000";
WHEN"0010"=>dout_temp<="1101101";
WHEN"0011"=>dout_temp<="1111001";
WHEN"0100"=>dout_temp<="0110011";
WHEN"0101"=>dout_temp<="1011011";
WHEN"0110"=>dout_temp<="1011111";
WHEN"0111"=>dout_temp<="1110000";
WHEN"1000"=>dout_temp<="1111111";
WHEN"1001"=>dout_temp<="1111011";
WHENOTHERS=>dout_temp<="1001111";
ENDCASE;
ENDPROCESS;
a<=dout_temp(6);
b<=dout_temp(5);
c<=dout_temp(4);
d<=dout_temp(3);
e<=dout_temp
(2);
f<=dout_temp
(1);
g<=dout_temp(0);
ENDaa2;
5.数据选择器
1)条件信号赋值语句
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux4IS
PORT(i0,i1,i2,i3,a,b:
INSTD_LOGIC;
q:
OUTSTD_LOGIC);
ENDmux4;
ARCHITECTUREarch1OFmux4IS
SIGANLsel:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
sel<=a&b;
q<=i0WHENsel="00"ELSE
i1WHENsel="01"ELSE
i2WHENsel="10"ELSE
i3WHENsel="11"ELSE
'X';
ENDarch1;
2)选择信号赋值语句
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux4IS
PORT(i0,i1,i2,i3,a,b:
INSTD_LOGIC;
q:
OUTSTD_LOGIC);
ENDmux4;
ARCHITECTUREarch2OFmux4IS
SIGANLsel:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
sel<=a&b;
WITHselSELECT
q<=i0WHEN"00",
i1WHEN"01",
i2WHEN"10",
i3WHEN"11",
'X'WHENOTHERS;
ENDarch2;
3)IF语句
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux4IS
PORT(i0,i1,i2,i3,a,b:
INSTD_LOGIC;
q:
OUTSTD_LOGIC);
ENDmux4;
ARCHITECTUREarch3OFmux4IS
SIGANLsel:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
sel<=a&b;
PROCESS(i0,i1,i2,i3,sel)
BEGIN
IF(sel="00")THEN
q<=i0;
ELSIF(sel="01")THEN
q<=i1;
ELSIF(sel="10")THEN
q<=i2;
ELSIF(sel="11")THEN
q<=i3;
ELSE
q<='X';
ENDIF;
ENDPROCESS;
ENDarch3;
4)CASE语句
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux4IS
PORT(a,b,i0,i1,i2,i3:
INSTD_LOGIC;
q:
OUTSTD_LOGIC);
ENDmux4;
ARCHITECTUREarch4OFmux4IS
SIGANLsel:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
sel<=a&b;
PROCESS(sel,i0,i1,i2,i3)
CASEselIS
WHEN"00"=>q<=i0;
WHEN"01"=>q<=i1;
WHEN"10"=>q<=i2;
WHEN"11"=>q<=i3;
WHENOTHERS=>q<='X';
ENDCASE;
ENDPROCESS;
ENDarch4;
6.练习题
●两输入异或门(行为、数据流描述方式)
●数据分配器:
在地址选择信号(3路)的控制下,将输入的1路数据从多路输出(8路)中选择某一路输出。
二、时序逻辑电路的设计实例
●D触发器
●寄存器
●移位寄存器
●计数器
●练习题:
锁存器
1.D触发器
异步置零端、异步置1端:
只要信号有效(低电平有效),立即进行复位或置位操作,复位和置位操作与时钟信号无关。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYd_ffIS
PORT(clk,d:
INSTD_LOGIC;
s,r:
INSTD_LOGIC;
q,qb:
OUTSTD_LOGIC);
ENDd_ff;
ARCHITECTUREarchiOFd_ffIS
SIGNALtemp:
STD_LOGIC;
BEGIN
PROCESS(clk,r,s)
BEGIN
IFr='0'THEN
temp<='0';
ELSIFs='0'THEN
temp<='1';
ELSIF(clk'EVENTANDclk='1')THEN
temp<=d;
ENDIF;
ENDPROCESS;
q<=temp;
qb<=NOTtemp;
ENDarchi;
2.寄存器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYregisterIS
PORT(d:
INSTD_LOGIC_VECTOR(7DOWNTO0);
oe,clk:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDregister;
ARCHITECTUREarchiOFregisterIS
SIGNALq_tmp:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
PROCESS(clk,oe)
BEGIN
IF(oe='0')THEN
IF(clk'EVENTANDclk='1')THEN
q_tmp<=d;
ENDIF;
ELSE
q_tmp<=(OTHERS=>'Z');
ENDIF;
ENDPROCESS;
q<=q_tmp;
ENDarchi;
3.移位寄存器
在寄存器的基础上增加了移位功能,移位功能是指寄存器中所存储的二进制数据能够在时钟信号控制下依次进行左移或者右移。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYshift195IS
PORT(clr,sh_ld,cp,j,k:
INSTD_LOGIC;
d:
INSTD_LOGIC_VECTOR(3DOWNTO0);
q:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDshift195;
ARCHITECTUREarchiOFshift195IS
SIGNALq_tmp:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(clr,sh_ld,cp,j,k,d)
BEGIN
IF(clr='0')THEN
q_tmp<=''0000'';
ELSIF(cp'EVENTANDcp='1')THEN
IFsh_ld='0'THEN
q_tmp<=d;
ELSIF(j='0'ANDk='0')THEN
FORiIN0TO2LOOP
q_tmp(i+1)<=q_tmp(i);
ENDLOOP;
q_tmp(0)<='0';
ELSIF(j='0'ANDk='1')THEN
FORiIN0TO2LOOP
q_tmp(i+1)<=q_tmp(i);
ENDLOOP;
q_tmp(0)<=q_tmp(0);
ELSIF(j='1'ANDk='0')THEN
FORiIN0TO2LOOP
q_tmp(i+1)<=q_tmp(i);
ENDLOOP;
q_tmp(0)<=NOT(q_tmp(0));
ELSIF(j='1'ANDk='1')THEN
FORiIN0TO2LOOP
q_tmp(i+1)<=q_tmp(i);
ENDLOOP;
q_tmp(0)<='1';
ENDIF;
ENDIF;
ENDPROCESS;
q<=q_tmp;
ENDarchi;
4.计数器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
--定义了很多新的函数,可以允许STD_LOGIC类型和整数类型之间的算术运算
ENTITYcounterIS
PORT(clk,clr,updown,load:
INSTD_LOGIC;
d:
INSTD_LOGIC_VECTOR(2DOWNTO0);
q:
BUFFERSTD_LOGIC_VECTOR(2DOWNTO0));
ENDcounter;
ARCHITECTUREarchiOFcounterIS
BEGIN
PROCESS(clr,clk,load)
BEGIN
IFclr='0'THEN
q<=''000'';
ELSIFload='1'THEN
q<=d;
ELSIF(clk'EVENTANDclk='1')THEN
IF(updown='1')THEN
q<=q+1;
ELSE
q<=q-1;
ENDIF;
ENDIF;
ENDPROCESS;
ENDarchi;
5.练习题
锁存器:
当三态输出允许控制端有效,且使能控制信号有效时,输出信号才随着输入信号的变化而变化。
三、有限状态机的设计实例
●Moore型状态机
三进程描述方式
双进程描述方式1:
(次态逻辑+输出逻辑)、状态寄存器
双进程描述方式2:
(次态逻辑+状态寄存器)、输出逻辑
双进程描述方式3:
次态逻辑、(状态寄存器+输出逻辑)
●Mealy型状态机
双进程描述方式:
(次态逻辑+状态寄存器)、输出逻辑
练习题:
双进程描述—(次态逻辑+输出逻辑)、状态寄存器
1、存储控制器——Moore型状态机
1)三进程描述方式
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYstore_controllerIS
PORT(clk:
INSTD_LOGIC;
ready:
INSTD_LOGIC;
read_write:
INSTD_LOGIC;
we,oe:
OUTSTD_LOGIC);
ENDstore_controller;
ARCHITECTUREstate_machineOFstore_controllerIS
TYPEstate_typeIS(idle,decision,read,write);
SIGNALpresent_state,next_state:
state_type;
BEGIN
nextstate_logic:
PROCESS(present_state,ready,read_write)
BEGIN
CASEpresent_stateIS
WHENidle=>IFready='1'THEN
next_state<=decision;
ELSE
next_state<=idle;
ENDIF;
WHENdecision=>IFread_write='1'THEN
next_state<=read;
ELSE
next_state<=write;
ENDIF;
WHENread=>IFready='1'THEN
next_state<=idle;
ELSE
next_state<=read;
ENDIF;
WHENwrite=>IFready='1'THEN
next_state<=idle;
ELSE
next_state<=write;
ENDIF;
ENDCASE;
ENDPROCESSnextstate_logic;
state_register:
PROCESS(clk)
BEGIN
IF(clk'EVENTANDclk='1')THEN
present_state<=next_state;
ENDIF;
ENDPROCESSstate_register;
output_logic:
PROCESS