整理LCD计数显示程序.docx

整理LCD计数显示程序.docx

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整理LCD计数显示程序

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

----Uncommentthefollowinglibrarydeclarationifinstantiating

----anyXilinxprimitivesinthiscode.

--libraryUNISIM;

--useUNISIM.VComponents.all;

entitycounteris

Port（clk:

instd_logic;

resetn:

instd_logic;

dout:

outstd_logic_vector（7downto0）;

lcd_en:

outstd_logic;

lcd_rs:

outstd_logic;

lcd_rw:

outstd_logic）;

endcounter;

architectureBehavioralofcounteris

componentcounter60is

Port（clk:

instd_logic;

resetn:

instd_logic;

dout:

outstd_logic_vector（7downto0））;

endcomponent;

componentdecoderis

Port（din:

instd_logic_vector（3downto0）;

dout:

outstd_logic_vector（8downto0））;

endcomponent;

componentlcd_interfaceis

port（

clk:

instd_logic;

resetn:

instd_logic;

dout_s10:

instd_logic_vector（8downto0）;

dout_s1:

instd_logic_vector（8downto0）;

lcd_data:

outstd_logic_vector（7downto0）;

lcd_en:

outstd_logic;

lcd_rs:

outstd_logic;

lcd_rw:

outstd_logic

）;

endcomponent;

signalddout_s10:

std_logic_vector（8downto0）;

signalddout_s1:

std_logic_vector（8downto0）;

signalddout:

std_logic_vector（7downto0）;

begin

u1:

counter60portmap（clk,resetn,ddout）;

u2:

decoderportmap（ddout（7downto4）,ddout_s10）;

u3:

decoderportmap（ddout（3downto0）,ddout_s1）;

u4:

lcd_interfaceportmap（clk,resetn,ddout_s10,ddout_s1,dout,lcd_en,lcd_rs,lcd_rw）;

endBehavioral;

--------------------------------------------------------------------------------

--Company:

--Engineer:

--

--CreateDate:

13:

36:

1003/30/06

--DesignName:

--ModuleName:

count60-Behavioral

--ProjectName:

--TargetDevice:

--Toolversions:

--Description:

--

--Dependencies:

--

--Revision:

--Revision0.01-FileCreated

--AdditionalComments:

--

--------------------------------------------------------------------------------

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

entitycounter60is

Port（clk:

instd_logic;

resetn:

instd_logic;

dout:

outstd_logic_vector（7downto0））;

endcounter60;

architectureBehavioralofcounter60is

signalcount:

std_logic_vector（7downto0）;

signalcount_div:

std_logic_vector（25downto0）;

begin

dout<=count;

process（clk）

begin

if（clk'eventandclk='1'）then

if（resetn='0'）then

count_div<=（others=>'0'）;

elseif（count_div（25）='1'）then

count_div<=（others=>'0'）;

else

count_div<=count_div+1;

endif;

endif;

endif;

endprocess;

process（clk,resetn）

begin

ifresetn='0'then

count<=（others=>'0'）;

elsifrising_edge（clk）then

if（count_div（25）='1'）then

ifcount（3downto0）="1001"then

count（3downto0）<="0000";

count（7downto4）<=count（7downto4）+1;

else

count（3downto0）<=count（3downto0）+1;

endif;

ifcount="01011001"then

count<="00000000";

endif;

endif;

endif;

endprocess;

endBehavioral;

--------------------------------------------------------------------------------

--Company:

--Engineer:

--

--CreateDate:

13:

25:

3703/30/06

--DesignName:

--ModuleName:

decoder-Behavioral

--ProjectName:

--TargetDevice:

--Toolversions:

--Description:

--

--Dependencies:

--

--Revision:

--Revision0.01-FileCreated

--AdditionalComments:

--

--------------------------------------------------------------------------------

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

entitydecoderis

Port（din:

instd_logic_vector（3downto0）;--四位二进制码输入

dout:

outstd_logic_vector（8downto0））;--输出LED七段码

enddecoder;

architectureBehavioralofdecoderis

begin

process（din）

begin

casedinis

when"0000"=>dout<="100110000";--30

when"0001"=>dout<="100110001";--31

when"0010"=>dout<="100110010";--32

when"0011"=>dout<="100110011";--33

when"0100"=>dout<="100110100";--34

when"0101"=>dout<="100110101";--35

when"0110"=>dout<="100110110";--36

when"0111"=>dout<="100110111";--37

when"1000"=>dout<="100111000";--38

when"1001"=>dout<="100111001";--39

whenothers=>dout<="100100000";

endcase;

endprocess;

endBehavioral;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_arith.all;

useieee.std_logic_unsigned.all;

entitylcd_interfaceis

port（

clk:

instd_logic;

resetn:

instd_logic;

dout_s10:

instd_logic_vector（8downto0）;

dout_s1:

instd_logic_vector（8downto0）;

lcd_data:

outstd_logic_vector（7downto0）;

lcd_en:

outstd_logic;

lcd_rs:

outstd_logic;

lcd_rw:

outstd_logic

）;

endlcd_interface;

architecturelcd_interface_archoflcd_interfaceis

signallcd_we_n:

std_logic;

signallcd_en_int:

std_logic;

signal