数字系统设计与PLD应用答案Word格式.doc
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A—000B—001C—010D—011E—100
输出:
(2)“一对一”状态分配
次态表:
NS
PS
输入条件
A
Z
C
X
E
B
D
-
激励方程:
3.2、试给出一位全减器的算法描述和数据流描述
真值表:
x
y
bi
d
bo
1
x—被减数y—减数bi—低位向本位的借位d—差bo—本位向高位的借位
LIBRARYIEEE;
USEIEEE.Std_Logic_1164.ALL;
ENTITYfull_subIS
PORT(x,y,bi:
INStd_Logic;
d,bo:
OUTStd_Logic);
ENDfull_sub;
算法描述:
ARICHITECTUREalg_fsOFfull_subIS
BIGIN
PROCESS(x,y,bi)
BEGIN
IF(x=‘0’ANDy=‘0’ANDbi=‘0’ORx=‘1’ANDy=‘0’
ANDbi=‘1’ORx=‘1’ANDy=‘1’ANDbi=‘0’)THEN
bo<
=‘0'
;
d<
=‘0’;
ELSIF(x=‘1’ANDy=‘0’ANDbi=‘0’)THEN
=‘1’;
ELSIF(x=‘0’ANDy=‘1’ANDbi=‘1’)THEN
=‘1'
ELSE
ENDIF;
ENDPROCESSc1;
ENDalg_fs;
数据流描述:
(d=x⊕y⊕bibo=x’y+x’bi+ybi)
ARICHITECTUREdataflow_fsOFfull_subIS
BEGIN
d<
=xXORyXORbi;
bo<
=(NOTxANDy)OR(NOTxANDbi)
OR(yANDbi);
ENDdataflow_ha;
3.4、
(1).十进制-BCD码编码器,输入、输出均为低电平有效。
ENTITYencoderIS
PORT(a:
INStd_Logic_Vector(9DOWNTO0)
b:
OUTStd_Logic_Vector(3DOWNTO0));
ENDencoder;
ARCHITECTUREbeh_encoderOFencoderIS
WITHaSELECT
b<
=“0110”WHEN“0111111111”,
“0111”WHEN“1011111111”,
“1000”WHEN“1101111111”,
“1001”WHEN“1110111111”,
“1010”WHEN“1111011111”,
“1011”WHEN“1111101111”,
“1100”WHEN“1111110111”,
“1101”WHEN“1111111011”,
“1110”WHEN“1111111101”,
“1111”WHEN“1111111110”,
“0000”WHENOTHERS;
ENDbeh_encoder;
补充:
优先编码器
=“0110”WHEN“0XXXXXXXXX”,
“0111”WHEN“10XXXXXXXX”,
“1000”WHEN“110XXXXXXX”,
“1001”WHEN“1110XXXXXX”,
“1010”WHEN“11110XXXXX”,
“1011”WHEN“111110XXXX”,
“1100”WHEN“1111110XXX”,
“1101”WHEN“11111110XX”,
“1110”WHEN“111111110X”,
(2).时钟RS触发器。
ENTITYclk_rs_ffIS
PORT(r,s,cp:
INStd_Logic;
q,nq:
BUFFERStd_Logic);
ENDclk_rs_ff;
ARCHITECTUREbeh_clkrsffOFclk_rs_ffIS
ASSERTNOT(r=‘1‘ANDs=‘1'
)
REPORT"
Controlerror"
SEVERITYError;
PROCESS(r,s,cp)
IFcp=‘1’THEN
q<
=sOR(NOTrANDq);
nq<
=NOT(sOR(NOTrANDq));
ENDIF;
ENDPROCESS;
ENDbeh_clkrsff;
(3).带复位端、置位端、延迟为15ns的响应CP下降沿的JK触发器。
ENTITYjk_ffIS
GENERIC(tpd:
Time:
=15ns);
FORT(r,s,j,k,cp:
q,nq:
BUFFEERStd_Logic);
ENDjk_ff;
ARCHITECTUREbeh_jkffOFjk_ffIS
ASSERTNOT(r='
0‘ANDs='
0'
REPORT"
IFr=‘0’THEN
=‘0’AFTERtpd;
nq<
=‘1’AFTERtpd;
ELSIFs=‘0’THEN
ELSIF(cp’EventANDcp=‘0‘)THEN
=jANDnqORNOTkANDqAFTERtpd;
=NOT(jANDnqORNOTkANDq)AFTERtpd;
ENDIF;
ENDPROCESS;
ENDbeh_jkff;
(4).集成计数器74161。
USEIEEE.Std_Logic_Unsigned.ALL;
ENTITYcounter16IS
PORT(cr,ld,cp,ctt,ctp:
d:
INStd_Logic_Vector(3DOWNTO0);
q:
BUFFERStd_Logic_Vector(3DOWNTO0);
co:
OUTBit);
ENDcounter16;
ARCHITECTUREbehav_ctr16OFcounter16IS
PROCESS(cr,cp)
BEGIN
IFcr=‘0’THEN
q<
=“0000”;
ELSIF(cp’EventANDcp=‘1’)THEN
IFld=‘0’THEN
q<
=d;
ELSIF(ctt=‘1’ANDctp=‘1’)THEN
IFq=“1111”THEN
q<
ELSE
q<
=q+“0001”;
ENDIF;
ENDIF;
ENDIF;
ENDPROCES