1、A000 B001 C010 D011 E100输出:(2)“一对一”状态分配次态表:NSPS输入条件AZCXEBD-激励方程:3.2、试给出一位全减器的算法描述和数据流描述真值表:xybidbo1x被减数 y减数 bi低位向本位的借位 d差 bo本位向高位的借位LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY full_sub IS PORT(x, y,bi : IN Std_Logic; d,bo : OUT Std_Logic);END full_sub;算法描述:ARICHITECTURE alg_fs OF full_sub ISBIGI
2、N PROCESS(x,y,bi) BEGIN IF (x=0 AND y=0 AND bi=0 OR x=1 AND y=0 AND bi=1 OR x=1 AND y=1 AND bi=0 ) THEN bo=0; d=0; ELSIF (x=1 AND y=0 AND bi=0 ) THEN=1; ELSIF (x=0 AND y=1 AND bi=1 ) THEN=1 ELSE END IF; END PROCESS c1;END alg_fs;数据流描述:(d=xybi bo=xy+xbi+ybi)ARICHITECTURE dataflow_fs OF full_sub ISBEG
3、IN d=x XOR y XOR bi; bo=(NOT x AND y) OR (NOT x AND bi) OR (y AND bi);END dataflow_ha;3.4、(1).十进制-BCD码编码器,输入、输出均为低电平有效。ENTITY encoder ISPORT(a : IN Std_Logic_Vector(9 DOWNTO 0) b : OUT Std_Logic_Vector(3 DOWNTO 0);END encoder;ARCHITECTURE beh_encoder OF encoder IS WITH a SELECT b= “0110” WHEN “01111
4、11111”, “0111” WHEN “1011111111”, “1000” WHEN “1101111111”, “1001” WHEN “1110111111”, “1010” WHEN “1111011111”, “1011” WHEN “1111101111”, “1100” WHEN “1111110111”, “1101” WHEN “1111111011”, “1110” WHEN “1111111101”, “1111” WHEN “1111111110”, “0000” WHEN OTHERS;END beh_encoder;补充:优先编码器= “0110” WHEN “
5、0XXXXXXXXX”, “0111” WHEN “10XXXXXXXX”, “1000” WHEN “110XXXXXXX”, “1001” WHEN “1110XXXXXX”, “1010” WHEN “11110XXXXX”, “1011” WHEN “111110XXXX”, “1100” WHEN “1111110XXX”, “1101” WHEN “11111110XX”, “1110” WHEN “111111110X”,(2).时钟RS触发器。ENTITY clk_rs_ff IS PORT(r,s,cp:IN Std_Logic; q,nq : BUFFER Std_Logi
6、c);END clk_rs_ff ;ARCHITECTURE beh_clkrsff OF clk_rs_ff IS ASSERT NOT(r=1 AND s=1) REPORTControl error SEVERITY Error; PROCESS(r,s,cp) IF cp=1 THEN q= s OR (NOT r AND q); nq= NOT( s OR (NOT r AND q); END IF; END PROCESS;END beh_clkrsff;(3).带复位端、置位端、延迟为15ns的响应CP下降沿的JK触发器。ENTITY jk_ff IS GENERIC (tpd:
7、Time:=15 ns); FORT (r,s,j,k,cp: q,nq:BUFFEER Std_Logic);END jk_ff;ARCHITECTURE beh_jkff OF jk_ff IS ASSERT NOT(r=0 AND s=0 REPORT IF r=0 THEN=0 AFTER tpd; nq=1 AFTER tpd; ELSIF s=0 THEN ELSIF (cpEvent AND cp=0) THEN=j AND nq OR NOT k AND q AFTER tpd;=NOT( j AND nq OR NOT k AND q) AFTER tpd; END IF;
8、END PROCESS;END beh_jkff;(4).集成计数器74161。USE IEEE.Std_Logic_Unsigned.ALL;ENTITY counter16 IS PORT (cr, ld, cp, ctt, ctp : d : IN Std_Logic_Vector(3 DOWNTO 0); q : BUFFER Std_Logic_Vector(3 DOWNTO 0); co :OUT Bit);END counter16;ARCHITECTURE behav_ctr16 OF counter16 IS PROCESS (cr,cp) BEGIN IF cr=0 THEN q=“0000”; ELSIF (cpEvent AND cp=1) THEN IF ld=0 THEN q=d; ELSIF (ctt=1 AND ctp=1) THEN IF q=“1111” THEN q ELSE q=q+“0001”; END IF; END IF; END IF; END PROCES
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