海大EDA实验1参考答案.docx
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海大EDA实验1参考答案
LaboratoryExercise1
Switches,Lights,andMultiplexers
ED实验参与答案
Part1
libraryieee;
usepart1is
port（SW:
instd_logic_vector（17downto0）;
LEDR:
outstd_logic_vector（17downto0））;
endpart1;
architectureBehaviorofpart1is
begin
LEDR<=SW;
endBehavior;
part2
libraryieee;
use2to1multiplexerentity
entitymux21is
port（in_x,in_y,in_s:
instd_logic;
out_m:
outstd_logic）;
endmux21;
--a2to1multiplexerarchitecture
architecturestructuralofmux21is
signalu,v:
std_logic;
begin
u<=in_xand（notin_s）;
v<=in_yandin_s;
out_m<=uorv;
endstructural;
--aeight-bitwide2to1multiplexer
libraryieee;
usewide2to1multiplexerentity
entitymux21_8bitis
port（
SW:
instd_logic_vector（17downto0）;
--SW:
instd_logic_vector（15downto8）;
--SW:
instd_logic_vector（17downto17）;
LEDR:
outstd_logic_vector（7downto0））;
endmux21_8bit;
--eight-bitwide2to1multiplexerarchitecture
architectureStructuralofmux21_8bitis
componentmux21
port（in_x,in_y,in_s:
instd_logic;
out_m:
outstd_logic）;
endcomponent;
begin
U1:
mux21portmap（in_x=>SW（0）,in_y=>SW（8）,in_s=>SW（17）,out_m=>LEDR（0））;
U2:
mux21portmap（in_x=>SW
（1）,in_y=>SW（9）,in_s=>SW（17）,out_m=>LEDR
（1））;
U3:
mux21portmap（in_x=>SW
（2）,in_y=>SW（10）,in_s=>SW（17）,out_m=>LEDR
（2））;
U4:
mux21portmap（in_x=>SW（3）,in_y=>SW（11）,in_s=>SW（17）,out_m=>LEDR（3））;
U5:
mux21portmap（in_x=>SW（4）,in_y=>SW（12）,in_s=>SW（17）,out_m=>LEDR（4））;
U6:
mux21portmap（in_x=>SW（5）,in_y=>SW（13）,in_s=>SW（17）,out_m=>LEDR（5））;
U7:
mux21portmap（in_x=>SW（6）,in_y=>SW（14）,in_s=>SW（17）,out_m=>LEDR（6））;
U8:
mux21portmap（in_x=>SW（7）,in_y=>SW（15）,in_s=>SW（17）,out_m=>LEDR（7））;
endStructural;
part3
libraryieee;
use2to1multiplexerentity
entitymux21is
port（in_x,in_y,in_s:
instd_logic;
out_m:
outstd_logic）;
endmux21;
--a2to1multiplexerarchitecture
architecturestructuralofmux21is
signalsignal_u,signal_v:
std_logic;
begin
signal_u<=in_xand（notin_s）;
signal_v<=in_yandin_s;
out_m<=signal_uorsignal_v;
endstructural;
libraryieee;
use5to1multiplexerentity
entitymux51is
port（in5_u,in5_v,in5_w,in5_x,in5_y,in5_s1,in5_s2,in5_s0:
instd_logic;
out5_m:
outstd_logic）;
endmux51;
--a5to1multiplexerarchitecture
architectureStructuralofmux51is
componentmux21
port（in_x,in_y,in_s:
instd_logic;
out_m:
outstd_logic）;
endcomponent;
signalsignal_a,signal_b,signal_c:
std_logic;
begin
U1:
mux21portmap（in_x=>in5_u,in_y=>in5_v,in_s=>in5_s0,out_m=>signal_a）;
U2:
mux21portmap（in_x=>in5_w,in_y=>in5_x,in_s=>in5_s0,out_m=>signal_b）;
U3:
mux21portmap（in_x=>signal_a,in_y=>signal_b,in_s=>in5_s1,out_m=>signal_c）;
U4:
mux21portmap（in_x=>signal_c,in_y=>in5_y,in_s=>in5_s2,out_m=>out5_m）;
endStructural;
libraryieee;
use
--a3bit5to1multiplexerentity
entitymux51_3bitis
port（SW:
instd_logic_vector（17downto0）;
LEDR:
outstd_logic_vector（17downto0）;
LEDG:
outstd_logic_vector（2downto0））;
endmux51_3bit;
--a3bit5to1multiplexerarchitecture
architecturestructuralofmux51_3bitis
componentmux51
port（in5_u,in5_v,in5_w,in5_x,in5_y,in5_s1,in5_s2,in5_s0:
instd_logic;
out5_m:
outstd_logic）;
endcomponent;
begin
LEDR<=sw;
U1:
mux51portmap（in5_u=>SW（0）,in5_v=>SW（3）,in5_w=>SW（6）,in5_x=>SW（9）,in5_y=>SW（12）,
in5_s0=>SW（15）,in5_s1=>SW（16）,in5_s2=>SW（17）,out5_m=>LEDG（0））;
U2:
mux51portmap（in5_u=>SW
（1）,in5_v=>SW（4）,in5_w=>SW（7）,in5_x=>SW（10）,in5_y=>SW（13）,
in5_s0=>SW（15）,in5_s1=>SW（16）,in5_s2=>SW（17）,out5_m=>LEDG
（1））;
U3:
mux51portmap（in5_u=>SW
（2）,in5_v=>SW（5）,in5_w=>SW（8）,in5_x=>SW（11）,in5_y=>SW（14）,
in5_s0=>SW（15）,in5_s1=>SW（16）,in5_s2=>SW（17）,out5_m=>LEDG
（2））;
endstructural;
part4
libraryieee;
use7-segmentdecoderentity
entitydecoderis
port（decoder_in_3:
instd_logic_vector（2downto0）;
HEX0:
outstd_logic_vector（0to6））;
enddecoder;
--a7-segmentdecorderarchitecture
architecturebehavioralofdecoderis
begin
process（decoder_in_3）
begin
casedecoder_in_3is
when"000"=>HEX0<="0001001";
when"001"=>HEX0<="0000110";
when"010"=>HEX0<="1000110";
when"011"=>HEX0<="1000000";
whenothers=>Hex0<="1111111";
endcase;
endprocess;
endbehavioral;
part5
libraryieee;
usepart5is
port（SW:
instd_logic_vector（17downto0）;
HEX0,HEX1,HEX2,HEX3,HEX4:
outstd_logic_vector（6downto0））;
endpart5;
architectureBehaviorofpart5is
componentmux51_seg7
port（Mux51_seg7_in:
instd_logic_vector（17downto0）;
Seg:
outstd_logic_vector（6downto0））;
endcomponent;
begin
U0:
mux51_seg7portmap（Mux51_seg7_in=>SW,Seg=>HEX0）;
U1:
mux51_seg7portmap（Mux51_seg7_in（17downto15）=>SW（17downto15）,Mux51_seg7_in（14downto12）=>SW（11downto9）,
Mux51_seg7_in（11downto9）=>SW（8downto6）,Mux51_seg7_in（8downto6）=>SW（5downto3）,
Mux51_seg7_in（5downto3）=>SW（2downto0）,Mux51_seg7_in（2downto0）=>SW（14downto12）,
Seg=>HEX1）;
U2:
mux51_seg7portmap（Mux51_seg7_in（17downto15）=>SW（17downto15）,Mux51_seg7_in（14downto12）=>SW（8downto6）,
Mux51_seg7_in（11downto9）=>SW（5downto3）,Mux51_seg7_in（8downto6）=>SW（2downto0）,
Mux51_seg7_in（5downto3）=>SW（14downto12）,Mux51_seg7_in（2downto0）=>SW（11downto9）,
Seg=>HEX2）;
U3:
mux51_seg7portmap（Mux51_seg7_in（17downto15）=>SW（17downto15）,Mux51_seg7_in（14downto12）=>SW（5downto3）,
Mux51_seg7_in（11downto9）=>SW（2downto0）,Mux51_seg7_in（8downto6）=>SW（14downto12）,
Mux51_seg7_in（5downto3）=>SW（11downto9）,Mux51_seg7_in（2downto0）=>SW（8downto6）,
Seg=>HEX3）;
U4:
mux51_seg7portmap（Mux51_seg7_in（17downto15）=>SW（17downto15）,Mux51_seg7_in（14downto12）=>SW（2downto0）,
Mux51_seg7_in（11downto9）=>SW（14downto12）,Mux51_seg7_in（8downto6）=>SW（11downto9）,
Mux51_seg7_in（5downto3）=>SW（8downto6）,Mux51_seg7_in（2downto0）=>SW（5downto3）,
Seg=>HEX4）;
endBehavior;
-----------------------------------------------------------------------------------------------
-----------Acircuitthatcanselectanddisplayoneoffivecharacters------------------------
-----------------------------------------------------------------------------------------------
libraryieee;
usemux51_seg7is
port（Mux51_seg7_in:
instd_logic_vector（17downto0）;
Seg:
outstd_logic_vector（6downto0））;
endmux51_seg7;
architectureBehaviorofmux51_seg7is
componentmux51_3bit
port（S,U,V,W,X,Y:
instd_logic_vector（2downto0）;
M:
outstd_logic_vector（2downto0））;
endcomponent;
componentchar_7seg
port（C:
instd_logic_vector（2downto0）;
Display:
outstd_logic_vector（6downto0））;
endcomponent;
signalM:
std_logic_vector（2downto0）;
begin
M0:
mux51_3bitportmap（Mux51_seg7_in（17downto15）,Mux51_seg7_in（14downto12）,Mux51_seg7_in（11downto9）,
Mux51_seg7_in（8downto6）,Mux51_seg7_in（5downto3）,Mux51_seg7_in（2downto0）,M）;
H0:
char_7segportmap（M,Seg）;
endBehavior;
-----------------------------------------------------------------------------------------------
------------------------------a3bitmux5-----------------------------------------
-----------------------------------------------------------------------------------------------
libraryieee;
use2to1multiplexerentity
entitymux21is
port（in_x,in_y,in_s:
instd_logic;
out_m:
outstd_logic）;
endmux21;
--a2to1multiplexerarchitecture
architecturestructuralofmux21is
signalsignal_u,signal_v:
std_logic;
begin
signal_u<=in_xand（notin_s）;
signal_v<=in_yandin_s;
out_m<=signal_uorsignal_v;
endstructural;
libraryieee;
use5to1multiplexerentity
entitymux51is
port（in5_u,in5_v,in5_w,in5_x,in5_y,in5_s1,in5_s2,in5_s0:
instd_logic;
out5_m:
outstd_logic）;
endmux51;
--a5to1multiplexerarchitecture
architectureStructuralofmux51is
componentmux21
port（in_x,in_y,in_s:
instd_logic;
out_m:
outstd_logic）;
endcomponent;
signalsignal_a,signal_b,signal_c:
std_logic;
begin
U1:
mux21portmap（in_x=>in5_u,in_y=>in5_v,in_s=>in5_s0,out_m=>signal_a）;
U2:
mux21portmap（in_x=>in5_w,in_y=>in5_x,in_s=>in5_s0,out_m=>signal_b）;
U3:
mux21portmap（in_x=>signal_a,in_y=>signal_b,in_s=>in5_s1,out_m=>signal_c）;
U4:
mux21portmap（in_x=>signal_c,in_y=>in5_y,in_s=>in5_s2,out_m=>out5_m）;
endStructural;
-----------------------------------------------------------------------------------------------
------------------------------a3bit5to1multiplexer----------------------------------------
-----------------------------------------------------------------------------------------------
libraryieee;
use
--a3bit5to1multiplexerentity
entitymux51_3bitis
port（S,U,V,W,X,Y:
instd_logic_vector（2downto0）;
M:
outstd_logic_vector（2downto0））;
endmux51_3bit;
--a3bit5to1multiplexerarchitecture
architecturestructuralofmux51_3bitis
componentmux51
port（in5_u,in5_v,in5_w,in5_x,in5_y,in5_s1,in5_s2,in5_s0:
instd_logic;
out5_m:
outstd_logic）;
endcomponent;
begin
U1:
mux51portmap（in5_u=>U（0）,in5_v=>V（0）,in5_w=>W（0）,in5_x=>X（0）,in5_y=>Y（0）,
in5_s0=>S（0）,in5_s1=>S
（1）,in5_s2=>S
（2）,out5_m=>M（0））;
U2:
mux51portmap（in5_u=>U
（1）,in5_v=>V
（1）,in5_w=>W
（1）,in5_x=>X
（1）,in5_y=>Y
（1）,
in5_s0=>S（0）,in5_s1=>S
（1）,in5_s2=>S
（2）,out5_m=>M
（1））;
U3:
mux51portmap（in5_u=>U
（2）,in5_v=>V
（2）,in5_w=>W
（2）,in5_x=>X
（2）,in5_y=>Y
（2）,
in5
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