CPLD FPGA应用教案 09.docx
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CPLDFPGA应用教案09
课程名称:
CPLD/FPGA应用教师姓名:
刘丹丹
章节名称
硬件描述语言(VHDL)
专业/班级
12级自动化1班
教学目的要求
掌握 VHDL的描述风格,基本逻辑电路设计
教学重点
重点是理解VHDL不同描述风格的特点;
教学难点
掌握基本逻辑电路的VHDL描述设计方法。
课堂教学进程:
教学手段:
多媒体\实验箱\软件平台\仿真
9)十二进制同步计数器(10’)
引脚定义:
reset复位
en计数控制
clk时钟
qa,qb,qc,qd计数器输出
LIBRARYieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycount12is
port(clk,reset,en:
instd_logic;
qa,qb,qc,qd:
outstd_logic);
endcount12;
architecturebehaveofcount12is
signalcount_4:
std_logic_vector(3downto0);
begin
qa<=count_4(0);
qb<=count_4
(1);
qc<=count_4
(2);
qd<=count_4(3);
process(clk,reset)
begin
if(reset='0')then
count_4<="0000";
elsif(clk'eventandclk='1')then
if(en='1')then
if(count_4="1011")then
count_4<="0000";
else
count_4<=count_4+'1';
endif;
endif;
endif;
endprocess;
endbehave;
10)4位二进制可逆计数器(10’)
管脚定义:
reset复位
clk时钟
updn加减计数控制
qa,qb,qc,qd输出
LIBRARYieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityupdownis
port(clk,reset,updn:
instd_logic;
qa,qb,qc,qd:
outstd_logic);
endupdown;
architecturebehaveofupdownis
signalcount_6:
std_logic_vector(3downto0);
begin
qa<=count_6(0);
qb<=count_6
(1);
qc<=count_6
(2);
qd<=count_6(3);
process(clk,reset)
begin
if(reset='1')then
count_6<="000000";
elsif(clk'eventandclk='1')then
if(updn='1')then
count_6<=count_6+'1';
else
count_6<=count_6-'1';
endif;
endif;
endprocess;
endbehave;
11)可预置数的六十进制计数器(10’)
管脚定义:
clk时钟
bcd1wr个位预置数控制
bcd10wr十位预置数控制
datain预置数据
cin进位输入(计数脉冲)
co进位输出
bcd1p个位数据输出
bcd10p十位数据输出
LIBRARYieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycount60is
port(clk,bcd1wr,bcd10wr,cin:
instd_logic;
co:
outstd_logic;
datain:
instd_logic_vector(3downto0);
bcd1p:
outstd_logic_vector(3downto0);
bcd10p:
outstd_logic_vector(2downto0));
endcount60;
architecturebehaveofcount60is
signalbcd1n:
std_logic_vector(3downto0);
signalbcd10n:
std_logic_vector(2downto0);
begin
bcd1p<=bcd1n;
bcd10p<=bcd10n;
kk1:
process(clk,bcd1wr)
begin
if(bcd1wr='1')then
bcd1n<=datain;
elsif(clk'eventandclk='1')then
if(cin='1')then
if(bcd1n="1001")then
bcd1n<="0000";
else
bcd1n<=bcd1n+'1';
endif;
endif;
endif;
endprocesskk1;
kk2:
process(clk,bcd10wr)
begin
if(bcd10wr='1')then
bcd10n<=datain(2downto0);
elsif(clk'eventandclk='1')then
if(cin='1')and(bcd1n="1001")then
if(bcd10n="101")then
bcd10n<="000";
else
bcd10n<=bcd10n+'1';
endif;
endif;
endif;
endprocesskk2;
kk3:
process(bcd10n,bcd1n,cin)
begin
if(cin='1'andbcd1n="1001"andbcd10n="101")then
co<='1';
else
co<='0';
endif;
endprocesskk3;
endbehave;
12)各种计数器例(10’)
ENTITYcounterIS
PORT
(
d:
ININTEGERRANGE0TO255;--预置数据
clk:
INBIT;--时钟信号
clear:
INBIT;--计数器清零
ld:
INBIT;--计数器预置数
enable:
INBIT;--计数使能
up_down:
INBIT;--计数器加减控制
qa:
OUTINTEGERRANGE0TO255;--输出端
qb:
OUTINTEGERRANGE0TO255;:
qc:
OUTINTEGERRANGE0TO255;:
qd:
OUTINTEGERRANGE0TO255;
qe:
OUTINTEGERRANGE0TO255;
qf:
OUTINTEGERRANGE0TO255;
qg:
OUTINTEGERRANGE0TO255;
qh:
OUTINTEGERRANGE0TO255;
qi:
OUTINTEGERRANGE0TO255;
qj:
OUTINTEGERRANGE0TO255;
qk:
OUTINTEGERRANGE0TO255;
ql:
OUTINTEGERRANGE0TO255;
qm:
OUTINTEGERRANGE0TO255;
qn:
OUTINTEGERRANGE0TO255–输出端
);
ENDcounter;
ARCHITECTUREaOFcounterIS
BEGIN
--有使能端的计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
BEGIN
IF(clk'EVENTANDclk='1')THEN
IFenable='1'THEN
cnt:
=cnt+1;
ENDIF;
ENDIF;
qa<=cnt;
ENDPROCESS;
--同步预置数计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
BEGIN
IF(clk'EVENTANDclk='1')THEN
IFld='0'THEN
cnt:
=d;
ELSE
cnt:
=cnt+1;
ENDIF;
ENDIF;
qb<=cnt;
ENDPROCESS;
--同步清除计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
BEGIN
IF(clk'EVENTANDclk='1')THEN
IFclear='0'THEN
cnt:
=0;
ELSE
cnt:
=cnt+1;
ENDIF;
ENDIF;
qc<=cnt;
ENDPROCESS;
--加减计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
VARIABLEdirection:
INTEGER;
BEGIN
IF(up_down='1')THEN
direction:
=1;
ELSE
direction:
=-1;
ENDIF;
IF(clk'EVENTANDclk='1')THEN
cnt:
=cnt+direction;
ENDIF;
qd<=cnt;
ENDPROCESS;
--同步预置/计数控制计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
BEGIN
IF(clk'EVENTANDclk='1')THEN
IFld='0'THEN
cnt:
=d;
ELSE
IFenable='1'THEN
cnt:
=cnt+1;
ENDIF;
ENDIF;
ENDIF;
qe<=cnt;
ENDPROCESS;
--计数控制的加减计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
VARIABLEdirection:
INTEGER;
BEGIN
IF(up_down='1')THEN
direction:
=1;
ELSE
direction:
=-1;
ENDIF;
IF(clk'EVENTANDclk='1')THEN
IFenable='1'THEN
cnt:
=cnt+direction;
ENDIF;
ENDIF;
qf<=cnt;
ENDPROCESS;
--同步清除/计数控制计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
BEGIN
IF(clk'EVENTANDclk='1')THEN
IFclear='0'THEN
cnt:
=0;
ELSE
IFenable='1'THEN
cnt:
=cnt+1;
ENDIF;
ENDIF;
ENDIF;
qg<=cnt;
ENDPROCESS;
--同步预置/清除计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
BEGIN
IF(clk'EVENTANDclk='1')THEN
IFclear='0'THEN
cnt:
=0;
ELSE
IFld='0'THEN
cnt:
=d;
ELSE
cnt:
=cnt+1;
ENDIF;
ENDIF;
ENDIF;
qh<=cnt;
ENDPROCESS;
--同步预置/加减计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
VARIABLEdirection:
INTEGER;
BEGIN
IF(up_down='1')THEN
direction:
=1;
ELSE
direction:
=-1;
ENDIF;
IF(clk'EVENTANDclk='1')THEN
IFld='0'THEN
cnt:
=d;
ELSE
cnt:
=cnt+direction;
ENDIF;
ENDIF;
qi<=cnt;
ENDPROCESS;
--同步预置/计数控制/加减计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
VARIABLEdirection:
INTEGER;
BEGIN
IF(up_down='1')THEN
direction:
=1;
ELSE
direction:
=-1;
ENDIF;
IF(clk'EVENTANDclk='1')THEN
IFld='0'THEN
cnt:
=d;
ELSE
IFenable='1'THEN
cnt:
=cnt+direction;
ENDIF;
ENDIF;
ENDIF;
qj<=cnt;
ENDPROCESS;
--同步清除/预置/计数控制计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
BEGIN
IF(clk'EVENTANDclk='1')THEN
IFclear='0'THEN
cnt:
=0;
ELSE
IFld='0'THEN
cnt:
=d;
ELSE
IFenable='1'THEN
cnt:
=cnt+1;
ENDIF;
ENDIF;
ENDIF;
ENDIF;
qk<=cnt;
ENDPROCESS;
--同步清除/加减计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
VARIABLEdirection:
INTEGER;
BEGIN
IF(up_down='1')THEN
direction:
=1;
ELSE
direction:
=-1;
ENDIF;
IF(clk'EVENTANDclk='1')THEN
IFclear='0'THEN
cnt:
=0;
ELSE
cnt:
=cnt+direction;
ENDIF;
ENDIF;
ql<=cnt;
ENDPROCESS;
--同步清除/计数控制/加减计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
VARIABLEdirection:
INTEGER;
BEGIN
IF(up_down='1')THEN
direction:
=1;
ELSE
direction:
=-1;
ENDIF;
IF(clk'EVENTANDclk='1')THEN
IFclear='0'THEN
cnt:
=0;
ELSE
IFenable='1'THEN
cnt:
=cnt+direction;
ENDIF;
ENDIF;
ENDIF;
qm<=cnt;
ENDPROCESS;
Amodulus200upcounter
--模为200的计数器
PROCESS(clk)
VARIABLEcnt:
INTEGERRANGE0TO255;
CONSTANTmodulus:
INTEGER:
=200;
BEGIN
IF(clk'EVENTANDclk='1')THEN
IFcnt=modulusTHEN
cnt:
=0;
ELSE
cnt:
=cnt+1;
ENDIF;
ENDIF;
qn<=cnt;
ENDPROCESS;
ENDa;
13)直接调用小规模数字电路例(10’)
LIBRARYaltera;
USEaltera.maxplus2.ALL;--使用Altera的元件库
LIBRARYieee;
USEieee.std_logic_1164.ALL;
ENTITYcompinstIS
PORT
(
data,clock,clearn,presetn:
INSTD_LOGIC;
q_out:
OUTSTD_LOGIC;
a,b,c,gn:
INSTD_LOGIC;
d:
INSTD_LOGIC_VECTOR(7DOWNTO0);
y,wn:
OUTSTD_LOGIC
);
ENDcompinst;
ARCHITECTUREaOFcompinstIS
BEGIN
--D触发器
dff1:
dffPORTMAP(d=>data,q=>q_out,clk=>clock,clrn=>clearn,prn=>presetn);
--TTL74151
mux:
a_74151bPORTMAP(c,b,a,d,gn,y,wn);
ENDa;
14)选择信号(10’)
如果sel信号为”1”时,选择信号input1,否则选择信号input0.
ENTITYcondsigIS
PORT
(
input0,input1,sel:
INBIT;
output:
OUTBIT
);
ENDcondsig;
ARCHITECTUREmaxpldOFcondsigIS
BEGIN
output<=input0WHENsel='0'ELSEinput1;
ENDmaxpld;
15)三信号分别控制输出数值(10’)
输入信号high=1输出q=3
mid=1输出q=2
low=1输出q=1
ENTITYcondsigmIS
PORT
(
high,mid,low:
INBIT;
q:
OUTINTEGER
);
ENDcondsigm;
ARCHITECTUREmaxpldOFcondsigmIS
BEGIN
q<=3WHENhigh='1'ELSE--whenhigh
2WHENmid='1'ELSE--whenmidbutnothigh
1WHENlow='1'ELSE--whenlowbutnotmidorhigh
0;--whennotlow,mid,orhigh
ENDmaxpld;
16)由状态机方法描述的模4加减计数器(10’)
如果updown=0状态变化为:
zeroonetwothree
如果updown=1状态变化为:
zerothreetwoone
LIBRARYieee;
USEieee.std_logic_1164.ALL;
ENTITYenumsmchIS
PORT
(
updown:
INSTD_LOGIC;
clock:
INSTD_LOGIC;
lsb:
OUTSTD_LOGIC;
msb:
OUTSTD_LOGIC
);
ENDenumsmch;
ARCHITECTUREfirstenumsmchOFenumsmchIS
TYPEcount_stateis(zero,one,two,three);
ATTRIBUTEENUM_ENCODING:
STRING;
ATTRIBUTEENUM_ENCODINGOFcount_state:
TYPEIS"11011000";
SIGNALpresent_state,next_state:
count_state;
BEGIN
PROCESS(present_state,updown)
BEGIN
CASE