CPLD FPGA应用教案 09.docx

1、CPLD FPGA应用教案 09课程名称：CPLD/FPGA应用 教师姓名：刘丹丹章节名称硬件描述语言（VHDL）专业/班级12级自动化1班教学目的要求掌握VHDL的描述风格，基本逻辑电路设计教学重点重点是理解VHDL不同描述风格的特点；教学难点掌握基本逻辑电路的VHDL描述设计方法。课堂教学进程：教学手段:多媒体实验箱软件平台仿真9) 十二进制同步计数器(10)引脚定义: reset 复位 en 计数控制 clk 时钟 qa,qb,qc,qd 计数器输出 LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.

2、all;entity count12 isport(clk,reset,en: in std_logic; qa,qb,qc,qd: out std_logic);end count12;architecture behave of count12 issignal count_4: std_logic_vector(3 downto 0);begin qa=count_4(0); qb=count_4(1); qc=count_4(2); qd=count_4(3); process(clk,reset) begin if (reset=0) then count_4=0000; elsif

3、(clkevent and clk=1) then if(en=1) then if(count_4=1011) then count_4=0000; else count_4=count_4+1; end if; end if; end if; end process;end behave;10) 4位二进制可逆计数器(10)管脚定义: reset 复位 clk 时钟 updn 加减计数控制 qa,qb,qc,qd 输出LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity updown

4、isport(clk,reset,updn: in std_logic; qa,qb,qc,qd: out std_logic);end updown;architecture behave of updown issignal count_6: std_logic_vector(3 downto 0);begin qa=count_6(0); qb=count_6(1); qc=count_6(2); qd=count_6(3); process(clk,reset) begin if (reset=1) then count_6=000000; elsif(clkevent and clk

5、=1) then if(updn=1) then count_6=count_6+1; else count_6=count_6-1; end if; end if; end process;end behave;11)可预置数的六十进制计数器(10)管脚定义: clk 时钟 bcd1wr 个位预置数控制 bcd10wr 十位预置数控制 datain 预置数据 cin 进位输入(计数脉冲) co 进位输出 bcd1p 个位数据输出 bcd10p 十位数据输出LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.

6、all;entity count60 isport(clk,bcd1wr,bcd10wr,cin: in std_logic; co: out std_logic; datain: in std_logic_vector(3 downto 0); bcd1p: out std_logic_vector(3 downto 0); bcd10p: out std_logic_vector(2 downto 0);end count60;architecture behave of count60 issignal bcd1n: std_logic_vector(3 downto 0);signal

7、 bcd10n: std_logic_vector(2 downto 0);begin bcd1p=bcd1n; bcd10p=bcd10n; kk1: process(clk,bcd1wr) begin if (bcd1wr=1) then bcd1n=datain; elsif(clkevent and clk=1) then if (cin=1) then if(bcd1n=1001 ) then bcd1n=0000; else bcd1n=bcd1n+1; end if; end if; end if; end process kk1; kk2: process(clk,bcd10w

8、r) begin if (bcd10wr=1) then bcd10n=datain(2 downto 0); elsif(clkevent and clk=1) then if(cin=1) and (bcd1n=1001) then if(bcd10n=101) then bcd10n=000; else bcd10n=bcd10n+1; end if; end if; end if; end process kk2;kk3: process(bcd10n,bcd1n,cin) begin if(cin=1 and bcd1n=1001 and bcd10n=101) then co=1;

9、 else co=0; end if; end process kk3; end behave;12) 各种计数器例(10)ENTITY counter IS PORT ( d : IN INTEGER RANGE 0 TO 255; -预置数据 clk : IN BIT;-时钟信号 clear : IN BIT;-计数器清零 ld : IN BIT;-计数器预置数 enable : IN BIT;-计数使能 up_down : IN BIT;-计数器加减控制 qa : OUT INTEGER RANGE 0 TO 255;-输出端 qb : OUT INTEGER RANGE 0 TO 25

10、5; : qc : OUT INTEGER RANGE 0 TO 255; : qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255; qj : OUT INTEGER RANGE 0 TO 255; qk : OUT INTEGER RANGE 0 TO 2

11、55; ql : OUT INTEGER RANGE 0 TO 255; qm : OUT INTEGER RANGE 0 TO 255; qn : OUT INTEGER RANGE 0 TO 255 输出端 ); END counter;ARCHITECTURE a OF counter ISBEGIN - 有使能端的计数器 PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clkEVENT AND clk = 1) THEN IF enable = 1 THEN cnt := cnt + 1; END IF; E

12、ND IF; qa = cnt; END PROCESS; -同步预置数计数器 PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clkEVENT AND clk = 1) THEN IF ld = 0 THEN cnt := d; ELSE cnt := cnt + 1; END IF; END IF; qb = cnt; END PROCESS; -同步清除计数器 PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clkEVENT AND

13、clk = 1) THEN IF clear = 0 THEN cnt := 0; ELSE cnt := cnt + 1; END IF; END IF; qc = cnt; END PROCESS;-加减计数器 PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; VARIABLE direction : INTEGER; BEGIN IF (up_down = 1) THEN direction := 1; ELSE direction := -1; END IF; IF (clkEVENT AND clk = 1) THEN cnt

14、:= cnt + direction; END IF; qd = cnt; END PROCESS; -同步预置/计数控制计数器 PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clkEVENT AND clk = 1) THEN IF ld = 0 THEN cnt := d; ELSE IF enable = 1 THEN cnt := cnt + 1; END IF; END IF; END IF; qe = cnt; END PROCESS; -计数控制的加减计数器 PROCESS (clk) VARIABL

15、E cnt : INTEGER RANGE 0 TO 255; VARIABLE direction : INTEGER; BEGIN IF (up_down = 1) THEN direction := 1; ELSE direction := -1; END IF; IF (clkEVENT AND clk = 1) THEN IF enable = 1 THEN cnt := cnt + direction; END IF; END IF; qf = cnt; END PROCESS; -同步清除/计数控制计数器 PROCESS (clk) VARIABLE cnt : INTEGER

16、RANGE 0 TO 255; BEGIN IF (clkEVENT AND clk = 1) THEN IF clear = 0 THEN cnt := 0; ELSE IF enable = 1 THEN cnt := cnt + 1; END IF; END IF; END IF; qg = cnt; END PROCESS; -同步预置/清除计数器 PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clkEVENT AND clk = 1) THEN IF clear = 0 THEN cnt := 0; EL

17、SE IF ld = 0 THEN cnt := d; ELSE cnt := cnt + 1; END IF; END IF; END IF; qh = cnt; END PROCESS;-同步预置/加减计数器 PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; VARIABLE direction : INTEGER; BEGIN IF (up_down = 1) THEN direction := 1; ELSE direction := -1; END IF; IF (clkEVENT AND clk = 1) THEN IF ld

18、 = 0 THEN cnt := d; ELSE cnt := cnt + direction; END IF; END IF; qi = cnt; END PROCESS; -同步预置/计数控制/加减计数器 PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; VARIABLE direction : INTEGER; BEGIN IF (up_down = 1) THEN direction := 1; ELSE direction := -1; END IF; IF (clkEVENT AND clk = 1) THEN IF ld =

19、 0 THEN cnt := d; ELSE IF enable = 1 THEN cnt := cnt + direction; END IF; END IF; END IF; qj = cnt; END PROCESS; -同步清除/预置/计数控制计数器 PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clkEVENT AND clk = 1) THEN IF clear = 0 THEN cnt := 0; ELSE IF ld = 0 THEN cnt := d; ELSE IF enable = 1 THE

20、N cnt := cnt + 1; END IF; END IF; END IF; END IF; qk = cnt; END PROCESS; -同步清除/加减计数器 PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; VARIABLE direction : INTEGER; BEGIN IF (up_down = 1) THEN direction := 1; ELSE direction := -1; END IF; IF (clkEVENT AND clk = 1) THEN IF clear = 0 THEN cnt := 0;

21、 ELSE cnt := cnt + direction; END IF; END IF; ql = cnt; END PROCESS; -同步清除/计数控制/加减计数器 PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; VARIABLE direction : INTEGER; BEGIN IF (up_down = 1) THEN direction := 1; ELSE direction := -1; END IF; IF (clkEVENT AND clk = 1) THEN IF clear = 0 THEN cnt := 0

22、; ELSE IF enable = 1 THEN cnt := cnt + direction; END IF; END IF; END IF; qm = cnt; END PROCESS;A modulus 200 up counter-模为200的计数器 PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; CONSTANT modulus : INTEGER := 200; BEGIN IF (clkEVENT AND clk = 1) THEN IF cnt = modulus THEN cnt := 0; ELSE cnt :=

23、cnt + 1; END IF; END IF; qn data, q = q_out, clk = clock, clrn = clearn, prn = presetn); -TTL74151 mux : a_74151b PORT MAP (c, b, a, d, gn, y, wn);END a;14) 选择信号(10)如果sel信号为”1”时,选择信号input1,否则选择信号input0. ENTITY condsig IS PORT ( input0, input1, sel : IN BIT; output : OUT BIT );END condsig;ARCHITECTUR

24、E maxpld OF condsig ISBEGIN output = input0 WHEN sel = 0 ELSE input1; END maxpld;15) 三信号分别控制输出数值(10)输入信号high =1 输出q=3 mid=1 输出q=2 low=1 输出q=1ENTITY condsigm IS PORT ( high, mid, low : IN BIT; q : OUT INTEGER );END condsigm;ARCHITECTURE maxpld OF condsigm ISBEGINq = 3 WHEN high = 1 ELSE - when high 2

25、 WHEN mid = 1 ELSE - when mid but not high 1 WHEN low = 1 ELSE - when low but not mid or high 0; - when not low, mid, or high END maxpld;16) 由状态机方法描述的模4加减计数器(10)如果updown=0 状态变化为: zeroonetwothree如果updown=1 状态变化为: zerothreetwooneLIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY enumsmch IS PORT ( updown

26、 : IN STD_LOGIC; clock : IN STD_LOGIC; lsb : OUT STD_LOGIC; msb : OUT STD_LOGIC );END enumsmch;ARCHITECTURE firstenumsmch OF enumsmch IS TYPE count_state is (zero, one, two, three); ATTRIBUTE ENUM_ENCODING : STRING; ATTRIBUTE ENUM_ENCODING OF count_state : TYPE IS 11 01 10 00; SIGNAL present_state, next_state : count_state;BEGIN PROCESS (present_state, updown) BEGIN CASE