DSP Architectures.docx

DSP Architectures.docx

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DSPArchitectures

DSPArchitecturesSummary

Abstract:

Asfarasthefutureofcommunicationsisconcerned,wehaveseenthatthereisgreatdemandforaudioandvideodatatocomplement

text.Digitalsignalprocessing（DSP）isthesciencethatenablestraditionallyanalogaudioandvideosignalstobeprocesseddigitallyfortransmission,storage,reproductionandmanipulation.Inthispaper,wewillexplainthevariousDSParchitectures,andthendiscusstheTI’smainproducts,Atthelast,wewillgiveaexpectationofthearchitecturaldirectioninDSP.

Keyword:

DSPArchitecture,GPP,VLIW,SHARC

1Introduction

Inthelastfewyears,thefutureofcommunicationshasbeenlargelyinfluencedbytherapidgrowthofwirelesstelephony,theInternetandmobilecomputing.Thetraditionalpurposesofsignalprocessingsuchasmodems,musicsynthesisandnoisecancellation,whileimportant,havebeenovertakenbythenew-foundWebbasedapplications.Theseemergingtechnologies,especiallyintheareaofwirelesscommunicationsandInternetaudio/video,haveledtoa50%increaseinDSPprocessorshipmentsinlastyears.

Asaresultofthisrapidlyexpandingmarket,DSPvendorsarevyingforaneverlargersliceofthepie.Toenticeendproductmanufacturerstoadopttheirchipsaswellastomeettheneedsoftheemergingtechnologies,newinnovationsinDSPcapabilitiesarerequired.WewilllookatthetraditionalDSPaswellasthecurrentfeaturesandthehistoricalconceptsbehindtheDSParchitecture.

Likeitsmicroprocessorcounterpart,performanceisofgreatinterest.BenchmarkingprovidesacommonmeansforDSPuserstoevaluateandcompareDSPchipsinthemarket.TheseresultsshowthatDSPprocessorsarealsoboundedbytradeoffsintermsofspeed,powerandcomputationaltasks.

2DSPProcessorFundamentals

Intheliterature,thedefinitionofadigitalsignalprocessortakesmanyforms.Inastrictsense,aDSPisanymicroprocessorthatprocessesdigitallyrepresentedsignals.ADSPfilterforexample,takesoneormorediscreteinputs,xi[n],andproducesonecorrespondingoutput,y[n]forn....,-1,0,1,2,...,andi=1,...,N,wherenisthenthinputoroutputattimen,iistheithcoefficientandNisthelengthofthefilter.Ineffect,theDSPimplementsthediscrete-timesystem.Asitsnameimplies,itisassumedthattheremustbesomeformofpreprocessingifthesignalsareinthecontinuoustimedomain,andthisiseasilyaccomplishedbyananalogtodigital

converter（ADC）.

Ingeneral,DSPfunctionsaremathematicaloperationsonreal-timesignalsandarerepetitiveandnumericallyintensive.Samplesfromreal-timesignalscannumberinthemillionsandhencealargememorybandwidthisneeded.ItisbecauseofthisverynaturethatDSPprocessorsarecreatedwithanarchitectureunlikethoseofconventionalmicroprocessors.MostDSPalgorithmsarenotcomplicatedandonlyrequiremultiplyandaccumulatecalculations.Most,ifnotall,DSPprocessorshavecircuitrybuiltandhardwiredtoexecutethesecalculationsasfastaspossible.

2.1ProcessorArchitectures

Thesignalprocessingalgorithmsandfunctionsdefineasuitablearchitectureforimplementation.WeuseasimpleexampleofanFIRfilterasabasisforthebuildingblocksoftheDSParchitecture.OnealgorithmusedtocreateanFIRfilterusesadirectformortappeddelaylinestructurewithM+1taps.TheM+1mostrecentinputsamplesaresavedas"filterstates".AccordingtoEquation

（1）,

theproductsofeachfilterstatex（n-i）anditscorrespondingcoefficientciareaccumulatedoraddedtoproducethecurrentoutputsampley（n）.Wecan

alsousethesignalflowgraphasshowninFigure1torepresentthisalgorithm.Howeveritisnotclearastothesequenceofthecomputationssinceitlookslikealltheoperationscanbecarriedoutatthesametime.

Thiscannotbethecaseasoperationshavetofollowasequenceforproperalgorithmfunctionality.Itisalsonotstatedastowherethelocationsofthedataoperandsandcoefficientsarebeforetheyareusedinthecomputations.Thus,amoreaccuratepicturehastobeformedbyusingmicro-operationsattheregistertransferlevel（RTL）,sequencedtemporarilyfromlefttorightasseeninFigure2.

Figure1:

TappeddelaylinestructureofaFIRfilter.

Figure2:

RegistertransferlevelrepresentationofaFIRfilter.

Thedelayedinputsarestoredinthedatamemory,D1andthecoefficients,Co,cl,...C（M）arelocatedinthecoefficientmemory.Thecontentsofbothmemoriesarefetchedandmultipliedtogether.Theresult

isthenaddedtothetemporarymemory,T1.T1iswheretheresultsoftheprevioustapsarestored.Thiscycleisrepeatedwithadifferentcoefficientuntilcompletion,producingthefinalresultasy（n）.

WecanmakecertainassumptionsforafundementalgeneralpurposeDSParchitecture.FromourunderstandingofDSPalgorithms,weseethat

mostcomputationsaremultiplyandaddoperations.Lookingattheexamplefromtheprevioussection,wewillrequiremultiplememoryunitsforstorageofdifferentdataaswellasmemoryforthearithmeticoperationsequences.Registerscanserveastemporarystoragelocationsandbuseswillbeneededtoconnecttheseunitstogether.Atthispoint,thereadermaybetemptedtoaskhowthisdesignisdifferentfromageneralpurposemicroprocessor（GPP）.IfwerecaptheissuescentraltoaDSPfunction,mostDSPcalculationsarerepetitive,requirealargememorybandwidthandnumeric

precision,allexecutedinrealtime.OnemightalsoarguethatmodernGPPshaveclockspeedsandcyclesperintsruction（CPI）thatoutperformDSPprocessorsbutGPPshaveoperationsandprogramflexibilitythatareunecessaryforDSP.DSPsmustexecutetheirtasksefficientlywhilekeepingcost,powerconsumption,memoryusageanddevelopmenttimelow,especiallyintheageofmobilecomputing.

Sincemanysignalprocessingapplicationsprocessmillionsofsamplesofdataforeverysecondofoperation,theminimumsampleperiodisusuallymoreimportantthanthecomputationallatencyoftheprocessor.Wedefinethesampleperiodasthetimebetweeneachsequentialsampleoftheinputdata.Thetimedifferencebetweentheinputdataandtheresultofitscomputationisknownasthecomputationallatency.Oncetheinitialsampleiscalculatedwithacertainlatency,thesubsequentresultswill,however,beproducedatthesampleperiodrate.Asthenumberofcalculationsincreases,therelativelylargerlatencyoftheprocessorwillbenegligiblecomparedtothesamplerate.

3ProcessorEvolution

EventhoughDSPprocessorshaveseendramaticchangesthroughthepastcoupledecades,therearecertainfeaturescentraltomostDSPprocessorsinthemarkettoday.Wealreadyknowthattheseprocessors

needmultiplememorybankswithindependentbuses,butinaddition,specializedinstructionsets,addressingmodes,controlandperipheralsarealsorequired.

ItiswidelyknownintheindustrythatthegeneralDSParchitecturescanbedividedintothreeorfourcategoriesorgenerationsandwewilllookateachoftheminturn.WewillnotaddresscustomDSParchitecturesforspecificDSPalgorithmsinthispaper.

3.1EarlySingleChipDSPProcessors

ThefirstsinglechipprocessorswerethefoundationonwhichmodernDSPprocessorswerebuilt.Althoughmostofthemwerenotcommerciallysuccessful,manufacturerswerequicktolearnthepitfallssurroundingeachofthem.Itisalsointerestingtonotethatamongtheseearlychipvendors,onlyonehasmaintainedaDSPproductlinetothisday.

In1978,AMIreleaseda"SignalProcessingPeripheral"knownasthe$2811whichwasdesignedtooperatealongwithaGPPsuchasthe6800fromMotorola.The$2811'smainfunctionwastorelievetheburdenofperformingmathintensivesubroutinesfromthemainprocessor.Inshort,itbehavedasamathcoprocessorandwasneverusedinlargequantitiesinanyendproduct.

Ayearlater,Intelannouncedan"AnalogSignalProcessor"whichhadananalogtodigitalconverter（ADC）anddigitaltoanalogconverter（DAC）residingonthedie.Thedisadvantageofthisprocessor,2920,wasthatitdidnothaveatruemultiplier.Multiplicationwasaccomplishedbybitshiftingandaddingpartialproducts;thustheperformanceofthe2920wasonlysilghtlybetterthanaGPP.Commercially,thechipwasonlyusedinmodems.

3.2FirstGenerationConventional

ThisclassofarchitecturerepresentedthefirstwidelyacceptedDSPprocessorsinthemarket,appearingintheearly1980's.Therewereafew

keymanufacturersthatofferedprocessorsthatsharemanysimilartraits.ThechipsweredesignedaroundaHarvardarchitecturewithseparatedataandprogrambusesfortheindividualdataandprogrammemoriesrespectively.Thekeyfunctionalblockswerethemultiply,addandaccumulatorunits,but

theseprocessorscouldonlyperformfixed-pointcomputations.ThesoftwarethataccompaniedthechipshadspecializedinstructionsetsandaddressingmodesforDSPwithhardwaresupportforsoftwarelooping.

TheseprocessorsweretheTMS320C10fromTexasInstrumentsandtheADSP-2101fromAnalogDevices.AgraphicalrepresentationofthegeneralarchitectureisdepictedinFigure3.

Figure3：

FirstgenerationconventionalDSParchitecture

3.3SecondGenerationEnhancedConventional

Thenextstageofdevelopmentstartedinthelate1980's/early1990's,andvariantsofthisarchitecturehavelasteduntiltoday.Theseprocessorsretainmuchofthedesignofthefirstgenerationbutwithaddedfeaturessuchaspipelining,multiplearithmeticlogicunits（ALU）andaccumulatorstoenhanceperformance.Theadvantageinthisisthatmostprocessorsarecodecompatiblewiththeirpredecessorswhileprovidingspeedu