DSP Architectures.docx

1、DSP ArchitecturesDSP Architectures SummaryAbstract : As far as the future of communications is concerned, we have seen that there is great demand for audio and video data to complementtext. Digital signal processing (DSP) is the science that enables traditionally analog audio and video signals to be

2、 processed digitally for transmission, storage, reproduction and manipulation. In this paper, we will explain the various DSP architectures , and then discuss the TIs main products, At the last, we will give a expectation of the architectural direction in DSP.Keyword: DSP Architecture, GPP, VLIW, SH

3、ARC1 IntroductionIn the last few years, the future of communications has been largely influenced by the rapid growth of wireless telephony, the Internet and mobile computing. The traditional purposes of signal processing such as modems, music synthesis and noise cancellation, while important, have b

4、een overtaken by the new-found Web based applications. These emerging technologies, especially in the area of wireless communications and Internet audio/video, have led to a 50% increase in DSP processor shipments in last years.As a result of this rapidly expanding market, DSP vendors are vying for

5、an ever larger slice of the pie. To entice end product manufacturers to adopt their chips as well as to meet the needs of the emerging technologies, new innovations in DSP capabilities are required. We will look at the traditional DSP as well as the current features and the historical concepts behin

6、d the DSP architecture.Like its microprocessor counterpart, performance is of great interest. Benchmarking provides a common means for DSP users to evaluate and compare DSP chips in the market. These results show that DSP processors are also bounded by tradeoffs in terms of speed, power and computat

7、ional tasks.2 DSP Processor FundamentalsIn the literature, the definition of a digital signal processor takes many forms. In a strict sense, a DSP is any microprocessor that processes digitally represented signals. A DSP filter for example, takes one or more discrete inputs, xin, and produces one co

8、rresponding output, yn for n . . . . , -1, 0, 1, 2 , . . . ,and i = 1 , . . . , N, where n is the nth input or output at time n, i is the ith coefficient and N is the length of the filter. In effect, the DSP implements the discrete-time system. As its name implies, it is assumed that there must be s

9、ome form of preprocessing if the signals are in the continuous time domain, and this is easily accomplished by an analog to digitalconverter (ADC).In general, DSP functions are mathematical operations on real-time signals and are repetitive and numerically intensive. Samples from real-time signals c

10、an number in the millions and hence a large memory bandwidth is needed. It is because of this very nature that DSP processors are created with an architecture unlike those of conventional microprocessors. Most DSP algorithms are not complicated and only require multiply and accumulate calculations.

11、Most, if not all, DSP processors have circuitry built and hard wired to execute these calculations as fast as possible.2.1 Processor ArchitecturesThe signal processing algorithms and functions define a suitable architecture for implementation. We use a simple example of an FIR filter as a basis for

12、the building blocks of the DSP architecture. One algorithm used to create an FIR filter uses a direct form or tapped delay line structure with M + 1 taps. The M + 1 most recent input samples are saved as filter states. According to Equation (1),the products of each filter state x(n - i) and its corr

13、esponding coefficient ci are accumulated or added to produce the current output sample y(n). We canalso use the signal flow graph as shown in Figure 1 to represent this algorithm. However it is not clear as to the sequence of the computations since it looks like all the operations can be carried out

14、 at the same time.This cannot be the case as operations have to follow a sequence for proper algorithm functionality. It is also not stated as to where the locations of the data operands and coefficients are before they are used in the computations. Thus, a more accurate picture has to be formed by

15、using micro-operations at the register transfer level (RTL), sequenced temporarily from left to right as seen in Figure 2.Figure 1: Tapped delay line structure of a FIR filter.Figure 2: Register transfer level representation of a FIR filter.The delayed inputs are stored in the data memory,D1 and the

16、 coefficients, Co, c l , . . . C(M) are located in the coefficient memory. The contents of both memories are fetched and multiplied together. The resultis then added to the temporary memory, T1. T1 is where the results of the previous taps are stored.This cycle is repeated with a different coefficie

17、nt until completion, producing the final result as y(n).We can make certain assumptions for a fundemental general purpose DSP architecture. From our understanding of DSP algorithms, we see thatmost computations are multiply and add operations. Looking at the example from the previous section, we wil

18、l require multiple memory units for storage of different data as well as memory for the arithmetic operation sequences. Registers can serve as temporary storage locations and buses will be needed to connect these units together. At this point, the reader may be tempted to ask how this design is diff

19、erent from a general purpose microprocessor (GPP). If we recap the issues central to a DSP function, most DSP calculations are repetitive, require a large memory bandwidth and numericprecision, all executed in real time. One might also argue that modern GPPs have clock speeds and cycles per intsruct

20、ion (CPI) that outperform DSP processors but GPPs have operations and program flexibility that are unecessary for DSP. DSPs must execute their tasks efficiently while keeping cost, power consumption, memory usage and development time low, especially in the age of mobile computing.Since many signal p

21、rocessing applications process millions of samples of data for every second of operation, the minimum sample period is usually more important than the computational latency of the processor. We define the sample period as the time between each sequential sample of the input data. The time difference

22、 between the input data and the result of its computation is known as the computational latency. Once the initial sample is calculated with a certain latency, the subsequent results will , however, be produced at the sample period rate. As the number of calculations increases, the relatively larger

23、latency of the processor will be negligible compared to the sample rate.3 Processor EvolutionEven though DSP processors have seen dramatic changes through the past couple decades, there are certain features central to most DSP processors in the market today. We already know that these processorsneed

24、 multiple memory banks with independent buses, but in addition, specialized instruction sets, addressing modes, control and peripherals are also required.It is widely known in the industry that the general DSP architectures can be divided into three or four categories or generations and we will look

25、 at each of them in turn. We will not address custom DSP architectures for specific DSP algorithms in this paper.3.1 Early Single Chip DSP ProcessorsThe first single chip processors were the foundation on which modern DSP processors were built. Although most of them were not commercially successful,

26、 manufacturers were quick to learn the pitfalls surrounding each of them. It is also interesting to note that among these early chip vendors, only one has maintained a DSP product line to this day. In 1978, AMI released a Signal Processing Peripheral known as the $2811 which was designed to operate

27、along with a GPP such as the 6800 from Motorola. The $2811s main function was to relieve the burden of performing math intensive subroutines from the main processor. In short, it behaved as a math coprocessor and was never used in large quantities in any end product.A year later, Intel announced an

28、Analog Signal Processor which had an analog to digital converter (ADC) and digital to analog converter (DAC) residing on the die. The disadvantage of this processor, 2920, was that it did not have a true multiplier. Multiplication was accomplished by bit shifting and adding partial products; thus th

29、e performance of the 2920 was only silghtly better than a GPP. Commercially, the chip was only used in modems.3.2 First Generation ConventionalThis class of architecture represented the first widely accepted DSP processors in the market, appearing in the early 1980s. There were a fewkey manufacturer

30、s that offered processors that share many similar traits. The chips were designed around a Harvard architecture with separate data and program buses for the individual data and program memories respectively. The key functional blocks were the multiply, add and accumulator units, butthese processors

31、could only perform fixed-point computations. The software that accompanied the chips had specialized instruction sets and addressing modes for DSP with hardware support for software looping.These processors were the TMS320C10 from Texas Instruments and the ADSP-2101 from Analog Devices. A graphical

32、representation of the general architecture is depicted in Figure 3.Figure 3：First generation conventional DSP architecture3.3 Second Generation Enhanced ConventionalThe next stage of development started in the late 1980s/early 1990s, and variants of this architecture have lasted until today. These processors retain much of the design of the first generation but with added features such as pipelining, multiple arithmetic logic units (ALU) and accumulators to enhance performance. The advantage in this is that most processors are code compatible with their predecessors while providing speedu