design compiler.docx

design compiler.docx

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designcompiler

DesignCompilerTutorial

∙Introduction

∙Initialization

oLinux

oSolaris

∙ProjectSetup

oDirectoryStructure

oSetupFile.synopsys_dc.setup

▪ExampleSetupFile

∙SynthesisFlow

oSynthesisOverview

▪ReadingintheDesign

▪ConstrainingtheDesign

▪DefiningDesignEnvironment

▪OptimizingtheDesign

▪ArchitecturalOptimizations

▪Logic-LevelOptimizations

▪Gate-LevelOptimizations

oReportingandAnalyzingtheDesign

oSaveDesign

∙Examples

oModularRippleCarryAdder

▪RCADesignStructure

▪ReadingintheDesign

▪SavingtheElaboratedDesign

▪SettingtheConstraints

▪OptimizingtheDesign

▪DesignAnalysisandReporting

▪TimingAnalysis

▪StructureAnalysis

▪SavingtheDesign

o********Optimizations:

GroupingandUngrouping********

oAnAdderDesign

▪ReadingintheDesign

∙Summary

Introduction

RTLsynthesisisanautomateddesigntaskinwhichhigh-leveldesigndescriptionswritteninHardwareDescriptionLanguages（suchasVHDL,Verilog,orSystemVerilog）aretransformedintogate-levelnetlists.Gate-levelnetlistisbasicallyacircuitimplementationofthedesignmadeoflibrarycomponents（bothcombinationalandsequentialcells）availableinthetechnologylibraryandtheirinterconnections.Thenetlistisgeneratedbythesynthesistoolaccordingtotheconstraintssetbythedesigner.Figure1belowshowsanoverviewofthesynthesis.

FIGURE1:

Anoverviewofthesynthesis.

DesignCompilerisRTLSynthesistoolbySynopsys.ItsupportsUNIXplatformsandisinstalledonInstitute'scomputersystems（seehereforavailableversionsoneachplatform:

mustatikli/linux）.DesignCompilerisnotsupportedonWindowsplatform.

ThistutorialisintendedforuserswithnopreviousexperiencewithDesignCompiler.ItintroducesyouhowtosetupthesynthesistoolandthebasictasksoflogicsynthesiswithDesignCompiler:

analyzingandelaboratingthedesign,settingconstraints,optimizingthedesign,analyzingtheresults,andsavinggeneratednetlists.Specifically,thistutorialconsidersonlysynchronoussystemsandbasicsynthesistasks.Subjectsasasynchronoussystemsoradvancedsynthesistechniqueswillnotbediscussed.InadditiontoDesignCompiler,thistutorialintroducesthebasicsoftheDesignCompilerGUI（calledDesignVision）.

ThistutorialincludesseveralexampleswritteninVHDLbut,excludingafewcommandsusingVHDLspecificcommandoptions,allinformationshownherecanalsobeappliedwithdesignswritteninVerilogorSystemVerilog.ThistutorialwasmadebyusingDesignCompilerversion2007.03SP2onLinux.

Note:

theYFoundation（i.e.versionsstartingfromversion2007.03）introducedsomeimportantchangesinSynopsysDesingCompilertool:

∙ThetoolsupportsonlyXGmode.SupportforDBmodehasbeenremovedfromthetool.

∙ThetoolsupportsonlyDCTCLcommandlanguage.SupportforDCSHcommandlanguagehasbeenremovedfromthetool.

Therefore,thistutorialanditsexamplesconsideronlyDesignCompilerrunninginXGmodeusingDCTCLcommandlanguageeventhougholdertoolsarestillavailableandinstalledonInstitute'scomputersystems.

Initialization

InordertouseDesignCompiler,youmustsetupyourenvironmentcorrectly.Thisincludessettingupafewvariables,files,andlicensinginformationandcanbedonebysourcingthescriptsshownbelow.

Linux

First,checkthislinktofindouttheavailableversionsofsynthesistoolscurrentlyinstalledonLinuxmachines.Then,initializethetoolbyrunningtherespectivesourcescript.Youshouldalwaysselectthelatestversionavailableunlessyouhaveareasontouseanolderversion.

$source/share/tktprog/synopsys/syn-2007.03-SP2/syn.sh

Solaris

First,checkthislink（mustatikli）tofindouttheavailableversionsofsynthesistoolscurrentlyinstalledonSolarismachine.Then,initializethetoolbyrunningtherespectivesourcescript.OnSolarisplatformyoumayuseeither32-bitor64-bitbinaries.Youshouldalwaysselectthelatestversionavailableunlessyouhaveareasontouseanolderversion.

$source/opt/synopsys/syn-2007.03-SP2/syn32.sh

Aftersourcingthegivenscriptyoushouldseeamessagesimilartotheonebelow（theactualmessagemaydifferdependingonthetoolversionandplatform）indicatingthatthesourcescriptwasreadandyourenvironmentsetupcorrectly:

########################################################################

SYNOPSYSSynthesisTools

version2007.03-SP2（32bitbinaries）

------------------------

Thereisno/tmp/synopsys_cachedirectory...creatinganewone.

NOTE:

Bydefault,DesignCompilerisnowstartinginXGmode.Ifyou

wanttorevertbacktoDBmode,pleaseuse:

dc_shell-t-db_modeORdc_shell-tcl_mode-db_mode

RTFM:

synopsys_help&

readmanpages:

man

eg.manset_clock_uncertainty

Ensurethatyour.synopsys_dc.setupetc.isvalidforthisversion.

########################################################################

ProjectSetup

InstructionsforsettingupaprojectdirectoryandDesignCompilersetupfileforyourproject.

DirectoryStructure

Inordertokeepyourprojectdatawell-organizedandsafe,itisrecommendedtostorefilesineachprojectintoaseparateprojectdirectory.Thefollowingexampleproposesonepossibledirectorystructureforsmallprojects.

Theexamplebelowincludesanoptionalsimulationdirectory（SIM/）forModelSimwhichisnotneededintheseexercisesbutisshownasanexampleofwhatsortofsubdirectoriesmightbeneededinrealprojects.

/--projectdirectory

.synopsys_dc.setup--SynopsysDesignCompilerinitializationfile

modelsim.ini--ModelSiminitializationfile

SRC/--HDLsourcefiles

SYN/--synthesissubdirectory

DDC/--DesignCompilerdatabase

NETLIST/--mappedVerilog/VHDLnetlists

RPT/--reports

SCR/--synthesisscripts

WORK/--intermediatefilesfromsynthesistool

SIM/--simulationsubdirectory（notneededintheseexamples）

SCR/--simulationscripts

WORK/--ModelSimworkdirectory

Youmaycopythedirectorystructureshownaboveanduseitassuch,modifyitasyoulike,orcreateyourowndirectorystructureaccordingtoyourneedsforyourownprojects.Whicheverwayyouchoosedo,keepinmindthatconsistentandsimpledirectorystructurehelpsyoutoreuseyourcodefromdifferentprojectsandtoautomatesometasksinthedesignflow.

Notethatunlessotherwisestated,theexamplesinthistutorialassumethatthedirectorystructuredescribedaboveisused.

Setupfile.synopsys_dc.setup

The.synopsys_dc.setupfileisthesetupfileforSynopsys'DesignCompiler.Setupfileisusedforinitializingdesignparametersandvariables,declaredesignlibraries,andsoon.Shortly,thesetupfiledefinesthebehaviorofthetoolandisrequiredforsettingthetoolupcorrectly.ThecommandsinthisfileareexecutedwhenDesignCompilerisinvoked.Therearethreedifferentlocationsfromwherethisfileissearchedfor:

1.TheSynopsysrootdirectory（/admin/setup/）forsystem-widesettings

2.Yourhomedirectory（$HOME/）foruser-definedsettings

3.Thecurrentworkingdirectory（$PWD/）fordesign-specificsettings

Thefilesarereadintheordershownabove.Settingsinuser-specificsetupfileoverridethesettingsfromsystem-widesetupfileandsettingsindesign-specificsetupfileoverridessettingsfrombothsystem-wideanduser-specificsetupfile.Youshouldhaveatleastdesign-specificsetupfileforeachofyourprojects.

Examplesetupfile

Thefollowingshowsanexampleofaminimalsetupfileusingdctclsyntax.Theexamplesetupfilehasalsobeenadaptedtousethedirectorystructuredescribedabove:

#Minimal.synopsys_dc.setupfile

#DefinetheUMCL180GIIlibrary

setUMC/share/tktprog/IC/umc

setL180_GII${UMC}/L180_GII/core/UMCL18G212D3_1.0/design_compiler

#Definethelibrariesandsearchpath

setsearch_path[concat$search_path./SRC./SYN/SCR${L180_GII}]

settarget_library${L180_GII}/umcl18g212t3_tc_180V_25C.db

setsynthetic_librarydw_foundation.sldb

setlink_library[concat"*"$target_library$synthetic_library]

setsymbol_library${L180_GII}/umcl18g212t3.sdb

define_design_libWORK-path./SYN/WORK

Theexamplefiledoesthefollowing:

Setsthesearch_path

Ifafileisreferencedjustbyitsname（directorypathnotspecified）thenDesignCompilersearchesthefilefromthedirectoriesspecifiedbythesearch_pathvariable.Forexample,inthiscasethesearchorderis:

thecurrentdirectory（.）,Synopsysinstallationdirectories/libraries/syn,/dw/syn_ver,and/dw/sim_ver,andfinallythedirectories./SRCand./SYN/SCRintheprojectdirectoryandtheUMCtechnologylibrarydirectory.

Setsthetarget_library

ThetargetlibraryvariabledefinesthetechnologylibrarythatDesignCompilerusestobuildthecircuit.Thatis,duringtechnologymappingphaseDesignCompilerselectscomponentsfromthelibraryspecifiedwiththetargetlibraryvariabletobuildthegate-levelnetlist.Inthisexample,weareusingtheUMCL180GIIlibrarywhichcanbefoundfromthe${L180_GII}directory.

Setsthesynthetic_library

ThesyntheticlibraryvariablespecifiesthesyntheticorDesignWarelibraries.Thesesyntheticlibrariesaretechnology-independent,microarchitecture-leveldesignlibrariesprovidingimplementationsforvariousIPblocks.

∙NotethattheselibrariesaretighlyintegratedintotheSynopsyssynthesisenvironment（i.e.theycannotbeusedwithnon-Synopsyssynthesistools）.

Thestandard.sldbsyntheticlibrarywhichisautomaticallyincludedcontainsbasicimplementationsforthebuilt-inHDLoperators（adders,subtractors,comparatorsetc）.Thedw_