design compiler.docx

1、design compilerDesign Compiler Tutorial Introduction Initialization o Linuxo Solaris Project Setup o Directory Structureo Setup File .synopsys_dc.setup Example Setup File Synthesis Flow o Synthesis Overview Reading in the Design Constraining the Design Defining Design Environment Optimizing the Desi

2、gn Architectural Optimizations Logic-Level Optimizations Gate-Level Optimizations o Reporting and Analyzing the Designo Save Design Examples o Modular Ripple Carry Adder RCA Design Structure Reading in the Design Saving the Elaborated Design Setting the Constraints Optimizing the Design Design Analy

3、sis and Reporting Timing Analysis Structure Analysis Saving the Design o *Optimizations: Grouping and Ungrouping*o An Adder Design Reading in the Design SummaryIntroductionRTL synthesis is an automated design task in which high-level design descriptions written in Hardware Description Languages (suc

4、h as VHDL, Verilog, or SystemVerilog) are transformed into gate-level netlists. Gate-level netlist is basically a circuit implementation of the design made of library components (both combinational and sequential cells) available in the technology library and their interconnections. The netlist is g

5、enerated by the synthesis tool according to the constraints set by the designer. Figure 1 below shows an overview of the synthesis. FIGURE 1: An overview of the synthesis. Design Compiler is RTL Synthesis tool by Synopsys. It supports UNIX platforms and is installed on Institutes computer systems (s

6、ee here for available versions on each platform: mustatikli/ linux). Design Compiler is not supported on Windows platform. This tutorial is intended for users with no previous experience with Design Compiler. It introduces you how to set up the synthesis tool and the basic tasks of logic synthesis w

7、ith Design Compiler: analyzing and elaborating the design, setting constraints, optimizing the design, analyzing the results, and saving generated netlists. Specifically, this tutorial considers only synchronous systems and basic synthesis tasks. Subjects as asynchronous systems or advanced synthesi

8、s techniques will not be discussed. In addition to Design Compiler, this tutorial introduces the basics of the Design Compiler GUI (called Design Vision). This tutorial includes several examples written in VHDL but, excluding a few commands using VHDL specific command options, all information shown

9、here can also be applied with designs written in Verilog or SystemVerilog. This tutorial was made by using Design Compiler version 2007.03 SP2 on Linux. Note: the Y Foundation (i.e. versions starting from version 2007.03) introduced some important changes in Synopsys Desing Compiler tool: The tool s

10、upports only XG mode. Support for DB mode has been removed from the tool. The tool supports only DCTCL command language. Support for DCSH command language has been removed from the tool.Therefore, this tutorial and its examples consider only Design Compiler running in XG mode using DCTCL command lan

11、guage even though older tools are still available and installed on Institutes computer systems. InitializationIn order to use Design Compiler, you must set up your environment correctly. This includes setting up a few variables, files, and licensing information and can be done by sourcing the script

12、s shown below. LinuxFirst, check this link to find out the available versions of synthesis tools currently installed on Linux machines. Then, initialize the tool by running the respective source script. You should always select the latest version available unless you have a reason to use an older ve

13、rsion. $ source /share/tktprog/synopsys/syn-2007.03-SP2/syn.shSolarisFirst, check this link (mustatikli) to find out the available versions of synthesis tools currently installed on Solaris machine. Then, initialize the tool by running the respective source script. On Solaris platform you may use ei

14、ther 32-bit or 64-bit binaries. You should always select the latest version available unless you have a reason to use an older version. $ source /opt/synopsys/syn-2007.03-SP2/syn32.shAfter sourcing the given script you should see a message similar to the one below (the actual message may differ depe

15、nding on the tool version and platform) indicating that the source script was read and your environment set up correctly: # SYNOPSYS Synthesis Tools version 2007.03-SP2 (32 bit binaries) - - - - - - - - - - - - - - - - - - - - - - - -There is no /tmp/synopsys_cache directory. creating a new one.NOTE

16、: By default, Design Compiler is now starting in XG mode. If you want to revert back to DB mode, please use: dc_shell-t -db_mode OR dc_shell -tcl_mode -db_modeRTFM: synopsys_help & read man pages: man eg. man set_clock_uncertaintyEnsure that your .synopsys_dc.setup etc. is valid for this version.#Pr

17、oject SetupInstructions for setting up a project directory and Design Compiler setup file for your project. Directory StructureIn order to keep your project data well-organized and safe, it is recommended to store files in each project into a separate project directory. The following example propose

18、s one possible directory structure for small projects. The example below includes an optional simulation directory (SIM/) for ModelSim which is not needed in these exercises but is shown as an example of what sort of subdirectories might be needed in real projects. / - project directory .synopsys_dc

19、.setup - Synopsys Design Compiler initialization file modelsim.ini - ModelSim initialization file SRC/ - HDL source files SYN/ - synthesis subdirectory DDC/ - Design Compiler database NETLIST/ - mapped Verilog/VHDL netlists RPT/ - reports SCR/ - synthesis scripts WORK/ - intermediate files from synt

20、hesis tool SIM/ - simulation subdirectory (not needed in these examples) SCR/ - simulation scripts WORK/ - ModelSim work directoryYou may copy the directory structure shown above and use it as such, modify it as you like, or create your own directory structure according to your needs for your own pr

21、ojects. Whichever way you choose do, keep in mind that consistent and simple directory structure helps you to reuse your code from different projects and to automate some tasks in the design flow. Note that unless otherwise stated, the examples in this tutorial assume that the directory structure de

22、scribed above is used. Setup file .synopsys_dc.setupThe .synopsys_dc.setup file is the setup file for Synopsys Design Compiler. Setup file is used for initializing design parameters and variables, declare design libraries, and so on. Shortly, the setup file defines the behavior of the tool and is re

23、quired for setting the tool up correctly. The commands in this file are executed when Design Compiler is invoked. There are three different locations from where this file is searched for: 1. The Synopsys root directory (/admin/setup/) for system-wide settings 2. Your home directory ($HOME/) for user

24、-defined settings 3. The current working directory ($PWD/) for design-specific settings The files are read in the order shown above. Settings in user-specific setup file override the settings from system-wide setup file and settings in design-specific setup file overrides settings from both system-w

25、ide and user-specific setup file. You should have at least design-specific setup file for each of your projects. Example setup fileThe following shows an example of a minimal setup file using dctcl syntax. The example setup file has also been adapted to use the directory structure described above: #

26、 Minimal .synopsys_dc.setup file# Define the UMC L180 GII libraryset UMC /share/tktprog/IC/umcset L180_GII $UMC/L180_GII/core/UMCL18G212D3_1.0/design_compiler# Define the libraries and search pathset search_path concat $search_path ./SRC ./SYN/SCR $L180_GIIset target_library $L180_GII/umcl18g212t3_t

27、c_180V_25C.dbset synthetic_library dw_foundation.sldbset link_library concat * $target_library $synthetic_libraryset symbol_library $L180_GII/umcl18g212t3.sdbdefine_design_lib WORK -path ./SYN/WORKThe example file does the following: Sets the search_pathIf a file is referenced just by its name (dire

28、ctory path not specified) then Design Compiler searches the file from the directories specified by the search_path variable. For example, in this case the search order is: the current directory (.), Synopsys installation directories /libraries/syn, /dw/syn_ver, and /dw/sim_ver, and finally the direc

29、tories ./SRC and ./SYN/SCR in the project directory and the UMC technology library directory. Sets the target_libraryThe target library variable defines the technology library that Design Compiler uses to build the circuit. That is, during technology mapping phase Design Compiler selects components

30、from the library specified with the target library variable to build the gate-level netlist. In this example, we are using the UMC L180 GII library which can be found from the $L180_GII directory. Sets the synthetic_libraryThe synthetic library variable specifies the synthetic or DesignWare librarie

31、s. These synthetic libraries are technology-independent, microarchitecture-level design libraries providing implementations for various IP blocks. Note that these libraries are tighly integrated into the Synopsys synthesis environment (i.e. they cannot be used with non-Synopsys synthesis tools). The standard.sldb synthetic library which is automatically included contains basic implementations for the built-in HDL operators (adders, subtractors, comparators etc). The dw_