ri<=ri+'1';
ifxingqi1="0111"then
xingqi1<="0001";
elsexingqi1<=xingqi1+'1';
endif;
endif;
endif;
endif;
endprocess;
month<=yue;
year<=nian;
date<=ri;
xingqi<=xingqi1;
endbav;
Ⅰ、初始设为2012年1月12日星期4
Ⅱ、观察平年闰年2月不同显示
②7位矢量转换成BCD显示
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityyourname_zhuanhuanis
port（input:
instd_logic_vector（7downto0）;
output10,output1:
outstd_logic_vector（3downto0））;
end;
architecturebavofyourname_zhuanhuanis
signalq:
integerrange0to255;
signalb10,b1:
std_logic_vector（3downto0）;
signala,b:
integerrange0to9;
begin
process（input）
begin
q<=conv_integer（input）;
a<=（q/10）;
b<=（qmod10）;
b10<=conv_std_logic_vector（a,4）;
b1<=conv_std_logic_vector（b,4）;
endprocess;
output10<=b10;
output1<=b1;
endbav;
③按键切换模块分别在en=00,01,10的情况下显示时间，年月日，星期
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyourname_keyqiehuanis
port（key:
instd_logic;
en:
outstd_logic_vector（1downto0））;
endyourname_keyqiehuan;
architecturebehavofyourname_keyqiehuanis
signalen1:
std_logic_vector（1downto0）:
="11";
begin
process（key）
begin
ifkey'eventandkey='1'then
en1<=en1+'1';
endif;
endprocess;
en<=en1;
endbehav;
④切换选择输出模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyourname_dispxianshiis
port（en:
instd_logic_vector（1downto0）;
xingqi,a0,a1,a2,a3,a4,a5,b0,b1,b2,b3,b4,b5:
instd_logic_vector（3downto0）;
c0,c1,c2,c3,c4,c5:
outstd_logic_vector（3downto0））;
endyourname_dispxianshi;
architecturebehavofyourname_dispxianshiis
begin
process（en）
begin
ifen="00"then
c0<=a0;
c1<=a1;
c2<=a2;
c3<=a3;
c4<=a4;
c5<=a5;
elsifen="01"then
c0<=b0;
c1<=b1;
c2<=b2;
c3<=b3;
c4<=b4;
c5<=b5;
elsifen="11"then
c0<=xingqi;
endif;
endprocess;
endbehav;
4、分频模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyourname_divis
port（clk_2KHz:
instd_logic;
clk_1KHz,clk_5HZ,clk_1Hz:
outstd_logic）;
endyourname_div;
architecturebavofyourname_divis
signalclk1K,clk5,clk1:
std_logic;
signalcnt200:
integerrange0to199;
signalcnt1000:
integerrange0to999;
begin
process（clk_2KHz）
begin
ifclk_2KHz'eventandclk_2KHz='1'then
clk1K<=not（clk1K）;
endif;
endprocess;
process（clk1K）
begin
ifclk1K'eventandclk1K='1'then
ifcnt200=199then
cnt200<=0;
else
cnt200<=cnt200+1;
endif;
ifcnt200<100then
clk5<='1';
else
clk5<='0';
endif;
endif;
endprocess;
process（clk1K）
begin
ifclk1K'eventandclk1K='1'then
ifcnt1000=999then
cnt1000<=0;
else
cnt1000<=cnt1000+1;
endif;
ifcnt1000<500then
clk1<='1';
else
clk1<='0';
endif;
endif;
endprocess;
clk_1KHz<=clk1K;
clk_5Hz<=clk5;
clk_1Hz<=clk1;
endbav;
5、两位BCD码六十进制计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyourname_cnt60is
port（clk,preset:
instd_logic;
bcd10,bcd1:
bufferstd_logic_vector（3downto0）;
co:
outstd_logic）;
endyourname_cnt60;
architecturebavofyourname_cnt60is
signalco_1:
std_logic;
begin
process（clk,preset）
begin
ifpreset='0'then
bcd1<="0000";
else
ifclk'eventandclk='1'then
ifbcd1="1001"then
bcd1<="0000";
else
bcd1<=bcd1+'1';
endif;
endif;
endif;
endprocess;
process（clk,preset,bcd1）
begin
ifpreset='0'then
bcd10<="0000";
co_1<='0';
else
ifclk'eventandclk='1'then
ifbcd1="1000"andbcd10="0101"then
co_1<='1';
elsifbcd1="1001"andbcd10="0101"then
bcd10<="0000";
co_1<='0';
elsifbcd1="1001"then
bcd10<=bcd10+'1';
co_1<='0';
endif;
endif;
endif;
endprocess;
co<=notco_1;
endbav;
6、报时模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyourname_baoshiis
port（clk_2KHz,clk_1KHz,clk1Hz:
instd_logic;
bcd10S,bcd1S,bcd10M,bcd1M:
instd_logic_vector（3downto0）;
clkout:
outstd_logic）;
endyourname_baoshi;
architecturebavofyourname_baoshiis
signalclkout_1:
std_logic;
begin
process（bcd10S,bcd1S,bcd10M,bcd1M,clk_2KHz,clk_1KHz,clk1Hz）
begin
if（bcd10M="0101"andbcd1M="1001"）and（bcd10S="0101"）and（bcd1S>4）and（bcd1S<=9）then
ifclk1Hz='1'then
clkout_1<=clk_1KHz;
else
clkout_1<='Z';
endif;
elsif（bcd10M="0000"andbcd1M="0000"）and（bcd10S="0000"）and（bcd1S="0000"）then
ifclk1Hz='1'then
clkout_1<=clk_2KHz;
else
clkout_1<='Z';
endif;
else
clkout_1<='Z';
endif;
clkout<=clkout_1;
endprocess;
endbav;
7、12/24小时切换控制模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyourname_cnt12_24is
port（clk,contr12_24:
instd_logic;
bcd10,bcd1:
outstd_logic_vector（3downto0））;
endyourname_cnt12_24;
architecturebehavofyourname_cnt12_24is
typelyis（s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23）;
signalp,n:
ly;
signalb10,b1:
std_logic_vector（3downto0）;
begin
process（clk）
begin
ifclk'eventandclk='1'then
p<=n;
endif;
endprocess;
process（p,contr12_24）
begin
casepis
whens0=>ifcontr12_24='0'then
b10<="0000";
b1<="0000";
else
b10<="0001";
b1<="0010";
endif;
n<=s1;
whens1=>b10<="0000";
b1<="0001";
n<=s2;
whens2=>b10<="0000";
b1<="0010";
n<=s3;
whens3=>b10<="0000";
b1<="0011";
n<=s4;
whens4=>b10<="0000";
b1<="0100";
n<=s5;
whens5=>b10<="0000";
b1<="0101";
n<=s6;
whens6=>b10<="0000";
b1<="0110";
n<=s7;
whens7=>b10<="0000";
b1<="0111";
n<=s8;
whens8=>b10<="0000";
b1<="1000";
n<=s9;
whens9=>b10<="0000";
b1<="0101";
n<=s10;
whens10=>b10<="0001";
b1<="0000";
n<=s11;
whens11=>b10<="0001";
b1<="0001";
n<=s12;
whens12=>b10<="0001";
b1<="0010";
n<=s13;
whens13=>ifcontr12_24='0'then
b10<="0001";
b1<="0011";
else
b10<="0000";
b1<="0001";
endif;
n<=s14;
whens14=>ifcontr12_24='0'then
b10<="0001";
b1<="0100";
else
b10<="0000";
b1<="0010";
endif;
n<=s15;
whens15=>ifcontr12_24='0'then
b10<="0001";
b1<="0101";
else
b10<="0000";
b1<="0011";
endif;
n<=s16;
whens16=>ifcontr12_24='0'then
b10<="0001";
b1<="0110";
else
b10<="0000";
b1<="0100";
endif;
n<=s17;
whens17=>ifcontr12_24='0'then
b10<="0001";
b1<="0111";
else
b10<="0000";
b1<="0101";
endif;
n<=s18;
whens18=>ifcontr12_24='0'then
b10<="0001";
b1<="1000";
else
b10<="0000";
b1<="0110";
endif;
n<=s19;
whens19=>ifcontr12_24='0'then
b10<="0001";
b1<="1001";
else
b10<="0000";
b1<="0111";
endif;
n<=s20;
whens20=>ifcontr12_24='0'then
b10<="0010";
b1<="0000";
else
b10<="0000";
b1<="1000";
endif;
n<=s21;
whens21=>ifcontr12_24='0'then
b10<="0010";
b1<="0001";
else
b10<="0000";
b1<="1001";
endif;
n<=s22;
whens22=>ifcontr12_24='0'then
b10<="0010";
b1<="0010";
else
b10<="0001";
b1<="0000";
endif;
n<=s23;
whens23=>ifcontr12_24='0'then
b10<="0010";
b1<="0011";
else
b10<="0001";
b1<="0001";
endif;
n<=s
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