EDA基于VHDL的时钟设计报告.docx

1、EDA基于VHDL的时钟设计报告12/24小时数字钟设计顶层图12/24小时数字钟设计顶层图二、模块和程序1、计数器25000library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yourname_cnt25000 is port(clk:in std_logic; clkout:out std_logic);end yourname_cnt25000;architecture bav of yourname_cnt25000 is signal cnt:integer range 0 t

2、o 24999; begin process(clk) begin if clkevent and clk=1 then if cnt=24999 then cnt=0; else cnt=cnt+1; end if; if cnt12500 then clkout=1; else clkout=0; end if; end if; end process;end bav;2、去抖模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yourname_qudou isport(key_

3、in,clk_1kHz:in std_logic; key_out:out std_logic);end yourname_qudou;architecture behav of yourname_qudou is signal cnt20:integer range 0 to 19; begin process(clk_1kHz,key_in) begin if clk_1kHzevent and clk_1kHz=1 then if cnt20=19 then cnt20=0; key_out=key_in; else cnt20qm if (nian(0)=0) and (nian(1)

4、=0) then qm=29; else qmqmqmqmqmqmqmqmqmqmqmnull; end case ;end process;process(co,preset,xingqi1) begin if preset=0 then yue=00000001 ; nian=00001100; ri=00001100; xingqi1=0010; else if coevent and co=1 then if(ri=qm) then ri=00000001; if xingqi1=0111then xingqi1=0001; else xingqi1=xingqi1+1; end if

5、; if(yue=00001100)then yue=00000001;nian=nian+1; else yue=yue+1; end if; elsif(riqm) then ri=ri+1; if xingqi1=0111then xingqi1=0001; else xingqi1=xingqi1+1; end if; end if; end if; end if;end process; month=yue;year=nian; date=ri; xingqi=xingqi1;end bav;、初始设为2012年1月12日星期4、观察平年闰年 2月不同显示7位矢量转换成BCD显示li

6、brary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity yourname_zhuanhuan is port(input:in std_logic_vector(7 downto 0); output10,output1: out std_logic_vector(3 downto 0);end;architecture bav of yourname_zhuanhuan issignal q: integer range 0 to 25

7、5;signal b10,b1:std_logic_vector(3 downto 0);signal a,b:integer range 0 to 9;beginprocess(input)beginq=conv_integer(input);a=(q/10);b=(q mod 10);b10=conv_std_logic_vector(a,4);b1=conv_std_logic_vector(b,4);end process;output10=b10;output1=b1;end bav;按键切换模块 分别在en=00,01,10的情况下显示 时间，年月日，星期library ieee;

8、use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yourname_keyqiehuan isport(key :in std_logic;en:out std_logic_vector(1 downto 0);end yourname_keyqiehuan ;architecture behav of yourname_keyqiehuan issignal en1:std_logic_vector(1 downto 0):=11;beginprocess(key)beginif keyevent and k

9、ey=1thenen1=en1+1;end if;end process;en=en1;end behav;切换选择输出模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yourname_dispxianshi isport(en:in std_logic_vector(1 downto 0);xingqi,a0,a1,a2,a3,a4,a5,b0,b1,b2,b3,b4,b5:in std_logic_vector(3 downto 0);c0,c1,c2,c3,c4,c5:ou

10、t std_logic_vector(3 downto 0);end yourname_dispxianshi;architecture behav of yourname_dispxianshi isbegin process(en)beginif en=00then c0=a0; c1=a1; c2=a2; c3=a3; c4=a4; c5=a5; elsif en=01then c0=b0; c1=b1; c2=b2; c3=b3; c4=b4; c5=b5; elsif en=11 then c0=xingqi; end if;end process;end behav;4、分频模块l

11、ibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yourname_div is port(clk_2KHz:in std_logic; clk_1KHz,clk_5HZ,clk_1Hz:out std_logic);end yourname_div;architecture bav of yourname_div issignal clk1K,clk5,clk1: std_logic;signal cnt200: integer range 0 to 199;signal cnt100

12、0:integer range 0 to 999;begin process(clk_2KHz) begin if clk_2KHzevent and clk_2KHz=1 then clk1K=not(clk1K); end if; end process; process(clk1K) begin if clk1Kevent and clk1K=1 then if cnt200=199 then cnt200=0; else cnt200=cnt200+1; end if; if cnt200100 then clk5=1; else clk5=0; end if; end if; end

13、 process; process(clk1K) begin if clk1Kevent and clk1K=1 then if cnt1000=999 then cnt1000=0; else cnt1000=cnt1000+1; end if; if cnt1000500 then clk1=1; else clk1=0; end if; end if; end process; clk_1KHz=clk1K; clk_5Hz=clk5; clk_1Hz=clk1;end bav;5、两位BCD码六十进制计数器library ieee;use ieee.std_logic_1164.all

14、;use ieee.std_logic_unsigned.all;entity yourname_cnt60 is port(clk,preset:in std_logic; bcd10,bcd1:buffer std_logic_vector(3 downto 0); co:out std_logic);end yourname_cnt60;architecture bav of yourname_cnt60 issignal co_1: std_logic;begin process(clk,preset) begin if preset=0 then bcd1=0000; else if

15、 clkevent and clk=1 then if bcd1=1001 then bcd1=0000; else bcd1=bcd1+1; end if; end if; end if; end process; process(clk,preset,bcd1) begin if preset=0 then bcd10=0000; co_1=0; else if clkevent and clk=1 then if bcd1=1000and bcd10=0101 then co_1=1; elsif bcd1=1001 and bcd10=0101 then bcd10=0000; co_

16、1=0; elsif bcd1=1001 then bcd10=bcd10+1; co_1=0; end if; end if; end if; end process; co4) and (bcd1S=9) then if clk1Hz=1 then clkout_1=clk_1KHz; else clkout_1=Z; end if; elsif (bcd10M=0000 and bcd1M=0000) and (bcd10S=0000) and (bcd1S=0000) then if clk1Hz=1 then clkout_1=clk_2KHz; else clkout_1=Z; e

17、nd if; else clkout_1=Z; end if; clkout=clkout_1; end process;end bav; 7、12/24小时切换控制模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yourname_cnt12_24 is port(clk,contr12_24:in std_logic; bcd10,bcd1:out std_logic_vector(3 downto 0);end yourname_cnt12_24;architecture b

18、ehav of yourname_cnt12_24 is type ly is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23); signal p,n:ly; signal b10,b1:std_logic_vector(3 downto 0); begin process(clk) begin if clkevent and clk=1 then p if contr12_24=0 then b10=0000; b1=0000; else b10=0001; b1=0

19、010; end if; n b10=0000; b1=0001; n b10=0000; b1=0010; n b10=0000; b1=0011; nb10=0000; b1=0100; nb10=0000; b1=0101; nb10=0000; b1=0110; nb10=0000; b1=0111; nb10=0000; b1=1000; nb10=0000; b1=0101; nb10=0001; b1=0000; nb10=0001; b1=0001; nb10=0001; b1=0010; nif contr12_24=0 then b10=0001; b1=0011; els

20、e b10=0000; b1=0001; end if; nif contr12_24=0 then b10=0001; b1=0100; else b10=0000; b1=0010; end if; nif contr12_24=0 then b10=0001; b1=0101; else b10=0000; b1=0011; end if; nif contr12_24=0 then b10=0001; b1=0110; else b10=0000; b1=0100; end if; nif contr12_24=0 then b10=0001; b1=0111; else b10=00

21、00; b1=0101; end if; nif contr12_24=0 then b10=0001; b1=1000; else b10=0000; b1=0110; end if; nif contr12_24=0 then b10=0001; b1=1001; else b10=0000; b1=0111; end if; nif contr12_24=0 then b10=0010; b1=0000; else b10=0000; b1=1000; end if; nif contr12_24=0 then b10=0010; b1=0001; else b10=0000; b1=1001; end if; nif contr12_24=0 then b10=0010; b1=0010; else b10=0001; b1=0000; end if; nif contr12_24=0 then b10=0010; b1=0011; else b10=0001; b1=0001; end if; n=s