基于CPLD的三相多波形函数发生器的外文翻译资料.docx

基于CPLD的三相多波形函数发生器的外文翻译资料.docx

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基于CPLD的三相多波形函数发生器的外文翻译资料

1英文资料

（FromDIGITALDESIGNprinciples&practices,JohnF.Wakerly）

LanguageOverview

WhatisVHDL?

VHDLisaprogramminglanguagethathasbeendesignedandoptimizedfordescribingthebehaviorofdigitalsystems.

VHDLhasmanyfeaturesappropriatefordescribingthebehaviorofelectroniccomponentsrangingfromsimplelogicgatestocompletemicroprocessorsandcustomchips.FeaturesofVHDLallowelectricalaspectsofcircuitbehavior（suchasriseandfalltimesofsignals,delaysthroughgates,andfunctionaloperation）tobepreciselydescribed.TheresultingVHDLsimulationmodelscanthenbeusedasbuildingblocksinlargercircuits（usingschematics,blockdiagramsorsystem-levelVHDLdescriptions）forthepurposeofsimulation. 

VHDLisalsoageneral-purposeprogramminglanguage:

justashigh-levelprogramminglanguagesallowcomplexdesignconceptstobeexpressedascomputerprograms,VHDLallowsthebehaviorofcomplexelectroniccircuitstobecapturedintoadesignsystemforautomaticcircuitsynthesisorforsystemsimulation.LikePascal,CandC++,VHDLincludesfeaturesusefulforstructureddesigntechniques,andoffersarichsetofcontrolanddatarepresentationfeatures.Unliketheseotherprogramminglanguages,VHDLprovidesfeaturesallowingconcurrenteventstobedescribed.ThisisimportantbecausethehardwaredescribedusingVHDLisinherentlyconcurrentinitsoperation.

OneofthemostimportantapplicationsofVHDListocapturetheperformancespecificationforacircuit,intheformofwhatiscommonlyreferredtoasatestbench.TestbenchesareVHDLdescriptionsofcircuitstimuliandcorrespondingexpectedoutputsthatverifythebehaviorofacircuitovertime.TestbenchesshouldbeanintegralpartofanyVHDLprojectandshouldbecreatedintandemwithotherdescriptionsofthecircuit.

 Astandardlanguage

OneofthemostcompellingreasonsforyoutobecomeexperiencedwithandknowledgeableinVHDLisitsadoptionasastandardintheelectronicdesigncommunity.UsingastandardlanguagesuchasVHDLvirtuallyguaranteesthatyouwillnothavetothrowawayandrecapturedesignconceptssimplybecausethedesignentrymethodyouhavechosenisnotsupportedinanewergenerationofdesigntools.Usingastandardlanguagealsomeansthatyouaremorelikelytobeabletotakeadvantageofthemostup-to-datedesigntoolsandthatyouwillhaveaccesstoaknowledgebaseofthousandsofotherengineers,manyofwhomaresolvingproblemssimilartoyourown.

 AbriefhistoryofVHDL

VHDL,whichstandsforVHSIC（VeryHighSpeedIntegratedCircuit）HardwareDescriptionLanguage,wasdevelopedintheearly1980sasaspin-offofahigh-speedintegratedcircuitresearchprojectfundedbytheU.S.DepartmentofDefense.DuringtheVHSICprogram,researcherswereconfrontedwiththedauntingtaskofdescribingcircuitsofenormousscale（fortheirtime）andofmanagingverylargecircuitdesignproblemsthatinvolvedmultipleteamsofengineers.Withonlygate-leveldesigntoolsavailable,itsoonbecameclearthatbetter,morestructureddesignmethodsandtoolswouldbeneeded.

 Tomeetthischallenge,ateamofengineersfromthreecompanies?

IBM,TexasInstrumentsandIntermetrics?

werecontractedbytheDepartmentofDefensetocompletethespecificationandimplementationofanew,language-baseddesigndescriptionmethod.ThefirstpubliclyavailableversionofVHDL,version7.2,wasreleasedin1985.In1986,theInstituteofElectricalandElectronicsEngineers,Inc.（IEEE）waspresentedwithaproposaltostandardizethelanguage,whichitdidin1987aftersubstantialenhancementsandmodificationsweremadebyateamofcommercial,governmentandacademicrepresentatives.Theresultingstandard,IEEE1076-1987,isthebasisforvirtuallyeverysimulationandsynthesiproductsoldtoday.Anenhancedandupdatedversionofthelanguage,IEEE1076-1993,wasreleasedin1994,andVHDLtoolvendorshavebeenrespondingbyaddingthesenewlanguagefeaturestotheirproducts.

 AlthoughIEEEStandard1076definesthecompleteVHDLlanguage,thereareaspectsofthelanguagethatmakeitdifficulttowritecompletelyportabledesigndescriptions（descriptionsthatcanbesimulatedidenticallyusingdifferentvendors?

tools）.TheproblemstemsfromthefactthatVHDLsupportsmanyabstractdatatypes,butitdoesnotaddressthesimpleproblemofcharacterizingdifferentsignalstrengthsorcommonlyusedsimulationconditionssuchasunknownsandhigh-impedance.

 SoonafterIEEE1076-1987wasadopted,simulatorcompaniesbeganenhancingVHDLwithnew,non-standardtypestoallowtheircustomerstoaccuratelysimulatecomplexelectroniccircuits.Thiscausedproblemsbecausedesigndescriptionsenteredintoonesimulatorwereoftenincompatiblewithothersimulationenvironments.VHDLwasquicklybecominganonstandard.

Togetaroundtheproblemofnonstandarddatatypes,anotherstandardwasdevelopedbyanIEEEcommittee.Thisstandard,numbered1164,definesastandardpackage（aVHDLfeaturethatallowscommonlyuseddeclarationstobecollectedintoanexternallibrary）containingdefinitionsforastandardnine-valueddatatype.Thisstandarddatatypeiscalledstd_logic,andtheIEEE1164packageisoftenreferredtoastheStandardLogicpackage.

TheIEEE1076-1987andIEEE1164standardstogetherformthecompleteVHDLstandardinwidestusetoday.（IEEE1076-1993isslowlyworkingitswayintotheVHDLmainstream,butitdoesnotaddsignificantnewfeaturesforsynthesisusers.）

Standard1076.3（oftencalledtheNumericStandardorSynthesisStandard）definesstandardpackagesandinterpretationsforVHDLdatatypesastheyrelatetoactualhardware.Thisstandard,whichwasreleasedattheendof1995,isintendedtoreplacethemanycustom（nonstandard）packagesthatvendorsofsynthesistoolshavecreatedanddistributedwiththeirproducts.

 IEEEStandard1076.3doesforsynthesisuserswhatIEEE1164didforsimulationusers:

increasethepowerofStandard1076,whileatthesametimeensuringcompatibilitybetweendifferentvendors?

tools.The1076.3standardincludes,amongotherthings:

1）  AdocumentedhardwareinterpretationofvaluesbelongingtothebitandbooleantypesdefinedbyIEEEStandard1076,aswellasinterpretationsofthestd_ulogictypedefinedbyIEEEStandard1164.

2）  Afunctionthatprovides"don&care"or"wildcard"testingofvaluesbasedonthestd_ulogictype.Thisisofparticularuseforsynthesis,sinceitisoftenhelpfultoexpresslogicintermsof"don抰care"values.

3）  Definitionsforstandardsignedandunsignedarithmeticdatatypes,alongwitharithmetic,shift,andtypeconversionoperationsforthosetypes.

 Theannotationoftiminginformationtoasimulationmodelisanimportantaspectofaccuratedigitalsimulation.TheVHDL1076standarddescribesavarietyoflanguagefeaturesthatcanbeusedfortimingannotation.However,itdoesnotdescribeastandardmethodforexpressingtimingdataoutsideofthetimingmodelitself.

 Theabilitytoseparatethebehavioraldescriptionofasimulationmodelfromthetimingspecificationsisimportantformanyreasons.OneofthemajorstrengthsofVerilogHDL（VHDL抯closestrival）isthefactthatVerilogHDLincludesafeaturespecificallyintendedfortimingannotation.Thisfeature,theStandardDelayFormat,orSDF,allowstimingdatatobeexpressedinatabularformandincludedintotheVerilogtimingmodelatthetimeofsimulation.

 TheIEEE1076.4standard,publishedbytheIEEEinlate1995,addsthiscapabilitytoVHDLasastandardpackage.Aprimaryimpetusbehindthisstandardeffort（whichwasdubbedVITAL,forVHDLInitiativeTowardASICLibraries）wastomakeiteasierforASICvendorsandotherstogeneratetimingmodelsapplicabletobothVHDLandVerilogHDL.Forthisreason,theunderlyingdataformatsofIEEE1076.4andVerilogSDFarequitesimilar.

WhenshouldyouuseVHDL?

WhychoosetouseVHDLforyourdesignefforts?

Therearemanylikelyreasons.IfyouaskmostVHDLtoolvendorsthisquestion,thefirstansweryouwillgetis,"Itwillimproveyourproductivity."Butjustwhatdoesthismean?

CanyoureallyexpecttogetyourprojectsdonefasterusingVHDLthanbyusingyourexistingdesignmethods?

 Theanswerisyes,butprobablynotthefirsttimeyouuseit,andonlyifyouapplyVHDLinastructuredmanner.VHDL（likeastructuredsoftwaredesignlanguage）ismostbeneficialwhenyouuseastructured,top-downapproachtodesign.Realincreasesinproductivitywillcomelater,whenyouhaveclimbedhigherontheVHDLlearningcurveandhaveaccumulatedalibraryofreusableVHDLcomponents.

 ProductivityincreaseswillalsooccurwhenyoubegintouseVHDLtoenhancecommunicationbetweenteammembersandwhenyoutakeadvantageofthemorepowerfultoolsforsimulationanddesignverificationthatareavailable.Inaddition,VHDLallowsyoutodesignatamoreabstractlevel.Insteadoffocusingonagate-levelimplementation,youcanaddressthebehavioralfunctionofthedesign.

HowwillVHDLincreaseyourproductivity?

Bymakingiteasytobuildanduselibrariesofcommonly-usedVHDLmodules.VHDLmakesdesignreusefeelnatural.Asyoudiscoverthebenefitsofreusablecode,youwillsoonfindyourselfthinkingofwaystowriteyourVHDLstatementsinwaysthatmakethemgeneralpurpose.Writingportablecodewillbecomeanautomaticreflex.

 AnotherimportantreasontouseVHDListherapidpaceofdevelopmentinelectronicdesignautomation（EDA）toolsandintargettechnologies.UsingastandardlanguagesuchasVHDLcangreatlyimproveyourchancesofmovingintomoreadvancedtools（forexample,fromabasiclow-costsimulatortoamoreadvancedone）