数字钟VHDL.docx
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数字钟VHDL
VHDL实验报告：
数字钟
一：
数字钟的功能
1：
具有以二十四小时计时、显示、整点报时、时间设置和闹钟的功能。
设计精度要求为1S。
二．功能描述
1.系统输入：
系统状态及校时、定时转换的控制信号为k、trans、set；时钟信号clk,采用1024Hz；系统复位信号reset。
输入信号均由按键产生。
系统输出：
LED显示输出，蜂鸣器声音信号输出。
2.计时：
正常工作状态下，每日按24h计时制计时并显示，蜂鸣器无声，逢整点报时。
3.校时：
在计时状态显示下，按下“set键”，进入“小时”校准状态，之后按下“k键”则进入“分”校准状态，继续按下“k键”则进入“秒复零”状态，第三次按下“k键”又恢复到正常计时显示状态。
A:
“小时”校准状态：
在“小时”校准状态下，显示“小时”数码管以1Hz的频率递增计数。
B:
“分”校准状态：
在“分”校准状态下，显示“分”的数码管以1Hz的频率递增计数。
C:
“秒”复零状态：
在“秒复零”状态下，显示“秒”的数码管复零。
4.整点报时：
蜂鸣器在“59”分钟的第“51”、“53”、“55”、“57‘秒发频率为512Hz的低音，在“59”分钟的第“59”秒发频率为1024Hz的高音，结束时为整点。
5.显示：
要求采用扫描显示方式驱动6个LED数码管显示小时、分、秒。
闹钟：
闹钟定时时间到，蜂鸣器发出周期为1s的“滴”、“滴”声，持续时间为10s；闹钟定时显示。
6.闹钟定时设置：
在闹钟定时显示状态下，按下“set键”，进入闹钟的“时”设置状态，之后按下“k键”进入闹钟的“分”设置状态，继续按下“k键”则进入“秒”设置状态，第三次按下“k键”又恢复到闹钟定时显示状态。
A:
闹钟“小时”设置状态：
在闹钟“小时”设置状态下，
显示“小时”的数码管以1Hz的频率递增计数。
B:
闹钟：
“分”设置状态：
在闹钟“分”设置状态下，显示“分”
的数码管以1Hz的频率递增计数。
三：
仿真。
分主控模块、计时校时模块、闹钟设定模块、选择显示模块、整点报时及闹铃模块、分频模块、动态显示模块。
1：
主控模块代码：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitycontrolis
port（clk,k,set,reset,trans:
instd_logic;
jh,jm,js,nh,nm,ns,flashh,flashm,flashs,selct:
outstd_logic）;
endcontrol;
architecturebehavofcontrolis
typestatesis（s0,s1,s2,s3,s4,s5,s6,s7）;
signalcurrent_state,next_state:
states;
begin
process（reset,clk,next_state,current_state,k,set）
begin
if（reset='1'）then
current_state<=s0;
elsif（clk'eventandclk='1'）then
current_state<=next_state;
endif;
casecurrent_stateis
whens0=>
flashh<='0';flashm<='0';flashs<='0';jh<='0';jm<='0';js<='0';nh<='0';nm<='0';ns<='0';selct<='1';
if（trans='1'）thennext_state<=s4;
elsif（set='1'）then
next_state<=s1;
else
next_state<=s0;
endif;
whens1=>
flashh<='1';flashm<='0';flashs<='0';jh<='1';jm<='0';js<='0';nh<='0';nm<='0';ns<='0';selct<='1';
if（set='1'）then
next_state<=s2;
else
next_state<=s1;
endif;
whens2=>
flashh<='0';flashm<='1';flashs<='0';jh<='0';jm<='1';js<='0';nh<='0';nm<='0';ns<='0';selct<='1';
if（set='1'）then
next_state<=s3;
else
next_state<=s2;
endif;
whens3=>
flashh<='0';flashm<='0';flashs<='1';jh<='0';jm<='0';js<='1';nh<='0';nm<='0';ns<='0';selct<='1';
if（set='1'）then
next_state<=s0;
else
next_state<=s3;
endif;
whens4=>
flashh<='0';flashm<='0';flashs<='0';jh<='0';jm<='0';js<='0';nh<='0';nm<='0';ns<='0';selct<='0';
if（trans='1'）then
next_state<=s0;
elsif（set='1'）then
next_state<=s5;
else
next_state<=s4;
endif;
whens5=>
flashh<='1';flashm<='0';flashs<='0';jh<='0';jm<='0';js<='0';nh<='1';nm<='0';ns<='0';selct<='0';
if（set='1'）then
next_state<=s6;
else
next_state<=s5;
endif;
whens6=>
flashh<='0';flashm<='1';flashs<='0';jh<='0';jm<='0';js<='0';nh<='0';nm<='1';ns<='0';selct<='0';
if（set='1'）then
next_state<=s7;
else
next_state<=s6;
endif;
whens7=>
flashh<='0';flashm<='0';flashs<='1';jh<='0';jm<='0';js<='0';nh<='0';nm<='0';ns<='1';selct<='0';
If（set='1'）then
next_state<=s4;
else
next_state<=s7;
endif;
endcase;
endprocess;
endbehav;
主控模块仿真图
2、计时校时模块（包括二选一，60进制及24进制部分）
二选一
libraryieee;
useieee.std_logic_1164.all;
entitymux2_1is
port（d0,d1,en:
instd_logic;
sel:
instd_logic;
y:
outstd_logic）;
endmux2_1;
architecturemux2_1_archofmux2_1is
begin
process（d0,d1,sel）
begin
if（sel='0'）then
y<=d0;
elsif（sel='1'anden='1'）then
y<=d1;
endif;
endprocess;
endmux2_1_arch;
六十进制计数
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycount_60is
port（clk:
instd_logic;
qh:
bufferstd_logic_vector（3downto0）;
ql:
bufferstd_logic_vector（3downto0）;
co:
bufferstd_logic）;
endcount_60;
architecturebehavofcount_60is
begin
process（clk）
begin
if（rising_edge（clk））then
if（qh="0101"andql="1001"）then
qh<="0000";co<='1';ql<="0000";
elsif（ql="1001"）then
ql<="0000";qh<=qh+1;co<='0';
else
ql<=ql+1;co<='0';
endif;
endif;
endprocess;
endbehav;
二十四进制计数
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycount_24is
port（clk:
instd_logic;
hh:
bufferstd_logic_vector（3downto0）;
hl:
bufferstd_logic_vector（3downto0））;
endcount_24;
architecturebehavofcount_24is
begin
process（clk）
begin
if（rising_edge（clk））then
if（hh="0010"andhl="0011"）then
hh<="0000";hl<="0000";
elsif（hl="1001"）then
hl<="0000";hh<=hh+1;
else
hl<=hl+1;
endif;
endif;
endprocess;
endbehav;
计时校时仿真图如下
3、闹钟设置模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityclksetis
port（hh,hl,mh,ml,sh:
instd_logic_vector（3downto0）;
nh,nm,ns,f4,k:
instd_logic;
bhg,bhd,bmg,bmd,bsg,bsd:
bufferstd_logic_vector（3downto0）;
comout:
outstd_logic）;
endclkset;
architecturebehavofclksetis
begin
com:
process（hh,mh,sh,hl,ml）
begin
if（bhg=hhandbhd=hlandbmg=mhandbmd=mlandbsg=sh）then
comout<='1';
else
comout<='0';
endif;
endprocess;
set:
process（f4）
begin
if（f4'eventandf4='1'）then
if（nh='1'andk='1'）then
if（bhg="0010"andbhd="0011"）then
bhd<="0000";bhg<="0000";
elsif（bhd="1001"）then
bhd<="0000";bhg<=bhg+1;
elsif（bhd<"1001"）then
bhd<=bhd+1;
endif;
endif;
endif;
endprocess;
process（f4）
begin
if（f4'eventandf4='1'）then
if（nm='1'andk='1'）then
if（bmg="0101"andbmd="1001"）then
bmd<="0000";bmg<="0000";
elsif（bmd="1001"）then
bmd<="0000";bmg<=bmg+1;
elsif（bmd<"1001"）then
bmd<=bmd+1;
endif;
endif;
endif;
endprocess;
process（f4）
begin
if（f4'eventandf4='1'）then
if（ns='1'andk='1'）then
if（bsg="0101"andbsd="1001"）then
bsd<="0000";bsg<="0000";
elsif（bsd="1001"）then
bsd<="0000";bsg<=bsg+1;
elsif（bsd<"1001"）then
bsd<=bsd+1;
endif;
endif;
endif;
endprocess;
endbehav;
4、选择显示控制模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitycompareis
port（hh,hl,mh,ml,sh,sl,bhg,bhd,bmg,bmd,bsg,bsd:
instd_logic_vector（3downto0）;
flashh,flashm,flashs,clk1,selct:
instd_logic;
shh,shl,smh,line,sml,ssh,ssl:
outstd_logic_vector（3downto0））;
endcompare;
architecturebehavofcompareis
begin
line<="1010";
process（clk1）
begin
ifselct='1'then
ssl<=sl;
ssh<=sh;
sml<=ml;
smh<=mh;
shl<=hl;
shh<=hh;
elsifselct='0'then
ssl<=bsd;
ssh<=bsg;
sml<=bmd;
smh<=bmg;
shl<=bhd;
shh<=bhg;
endif;
if（clk1='1'andflashs='1'）then
ssl<="1111";ssh<="1111";
endif;
if（clk1='1'andflashm='1'）then
sml<="1111";smh<="1111";
endif;
if（clk1='1'andflashh='1'）then
shl<="1111";shh<="1111";
endif;
endprocess;
endbehav;
5、整点报时及闹钟
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybaoshiis
port（mh,ml,sh,sl:
instd_logic_vector（3downto0）;
comout,f1024hz,f512hz,clk:
instd_logic;
bell:
outstd_logic）;
endbaoshi;
architecturebehavofbaoshiis
begin
process（clk,mh,ml,sh,sl,f1024hz,f512hz）
begin
if（comout='1'）then
bell<=clk;
elsif（mh="0101"andml="1001"）then
if（sh="0101"）then
if（sl="1001"）then
bell<=f1024hz;
elsif（sl="0001"orsl="0011"orsl="0101"orsl="0111"）then
bell<=f512hz;
endif;
else
bell<='0';
endif;
elsif（ml<"1001"ormh<"0101"orsh<"0101"）then
bell<='0';
endif;
endprocess;
endbehav;
6、分频模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpinis
port（clk:
instd_logic;
f512,f4,f1:
outstd_logic）;
endfenpin;
architecturefenoffenpinis
signalm:
std_logic_vector（9downto0）;
begin
process（clk）
begin
if（clk'eventandclk='1'）then
ifm="1111111111"then
m<="0000000000";
else
m<=m+'1';
endif;
endif;
f512<=m（0）;
f1<=m（9）;
f4<=m（7）;
endprocess;
endfen;
仿真图
7、动态显示模块
八选一
libraryieee;
useieee.std_logic_1164.all;
entitymux8_1is
port（D0,D1,D2,D3,D4,D5,D6,D7:
instd_logic_vector（3downto0）;
sel:
instd_logic_vector（2downto0）;
Q:
outstd_logic_vector（3downto0））;
endmux8_1;
architecturearchofmux8_1is
begin
process（D0,D1,D2,D3,D4,D5,D6,D7,SEL）
begin
caseselis
when"000"=>Q<=D0;
when"001"=>Q<=D1;
when"010"=>Q<=D2;
when"011"=>Q<=D3;
when"100"=>Q<=D4;
when"101"=>Q<=D5;
when"110"=>Q<=D6;
when"111"=>Q<=D7;
whenothers=>Q<="XXXX";
endcase;
endprocess;
endarch;
八进制计数器
libraryieee;
useieee.std_logic_1164.all;
entitymux8_1is
port（D0,D1,D2,D3,D4,D5,D6,D7:
instd_logic_vector（3downto0）;
sel:
instd_logic_vector（2downto0）;
Q:
outstd_logic_vector（3downto0））;
endmux8_1;
architecturearchofmux8_1is
begin
process（D0,D1,D2,D3,D4,D5,D6,D7,SEL）
begin
caseselis
when"000"=>Q<=D0;
when"001"=>Q<=D1;
when"010"=>Q<=D2;
when"011"=>Q<=D3;
when"100"=>Q<=D4;
when"101"=>Q<=D5;
when"110"=>Q<=D6;
when"111"=>Q<=D7;
whenothers=>Q<="XXXX";
endcase;
endprocess;
endarch;
数码管七段显示
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydeledis
port（num:
instd_logic_vector（3downto0）;
a,b,c,d,e,f,g:
outstd_logic）;
enddeled;
architectureartofdeledis
signalled:
std_logic_vector（6downto0）;
begin
process（num）
begin
casenumis
when"0000"=>led<="1111110";
when"0001"=>led<="0110000";
when"0010"=>led<="1101101";
when"0011"=>led<="1111001";
when"0100"=>led<="0110011";
when"0101"=>led<="1011011";
when"0110"=>led<="1011111";
when"0111"=>led<="1110000";
when"1000"=>led<="1111111";
when"1001"=>led<="1111011";
when"1111"=>led<="0000000";
whenothers=>led<="0000001";
endcase;
endprocess;
a<=led（6）;b<=led（5）;c<=led（4）;d<=led（3）;
e<=led
（2）;f<=led
（1）;g<=led（0）;
endart;
3-8译码器
libraryieee;
useieee.std_logic_1164.all;
entitydecode3_8is
port（a,b,c:
instd_logic;
s1,s2,s3:
instd_logic;
y:
outstd_logic_vector（7downto0））;
enddecode3_8;
architecturertlofdecode3_8is
signalind:
std_logic_vector（2downto0）;
begin
ind<=c&b&a;
process（ind,s1,s2,s3）
begin
if（s1='1'ands2='0'ands3='0'）then
caseindis
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