数电实验.docx
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数电实验
实验2、3quartus原理图设计
原理图:
仿真波形:
实验4
BCD码-七段译码器:
moduledecode4_7(codeout,indec);
input[3:
0]indec;
outputreg[6:
0]codeout;
always@(indec)
begin
case(indec)
4'd0:
codeout=7'b1111110;
4'd1:
codeout=7'b0110000;
4'd2:
codeout=7'b1101101;
4'd3:
codeout=7'b1111001;
4'd4:
codeout=7'b0110011;
4'd5:
codeout=7'b1011011;
4'd6:
codeout=7'b1011111;
4'd7:
codeout=7'b1110000;
4'd8:
codeout=7'b1111111;
4'd9:
codeout=7'b1111011;
default:
codeout=7'bx;
endcase
end
endmodule
一位数值比较器:
moduleFILE2(a_gt,a_eq,a_lt,a,b);
inputa,b;
outputa_gt,a_eq,a_lt;
assigna_gt=a&~b;
assigna_eq=a&b|~a&~b;
assigna_lt=~a&b;
endmodule
电路图:
仿真波形:
比较器
译码器:
实验5集成触发器应用及彩灯控制器
原理图:
JK触发器:
JKFF
仿真波形:
实验67位左移移位寄存器
原理图:
仿真波形:
实验7
88进制可逆计数器
modulell1536(data,CP,CR,CNT_EN,S1,S0,q_low,q_high,Cup,Cdown);
inputCP,CR;
inputCNT_EN,S1,S0;
input[7:
0]data;
outputreg[3:
0]q_low;
outputreg[3:
0]q_high;
outputwireCup,Cdown;
always@(posedgeCPornegedgeCR)
begin
if(~CR)
begin
q_low<=4'd0;
q_high<=4'd0;
end
elseif(CNT_EN)
begin
case({S1,S0})
2'b11:
begin
{q_high,q_low}<=data;
end
2'b10:
begin
if(q_low<4'd9)q_low<=q_low+1'd1;
else
begin
q_low<=4'd0;
q_high<=q_high+1'd1;
end
if((q_high==4'd8)&&(q_low==4'd7))
begin
q_low<=4'd0;
q_high<=4'd0;
end
end
2'b01:
begin
if(q_low>4'd0)q_low<=q_low-1'd1;
else
begin
q_low<=4'd9;
q_high<=q_high-1'd1;
end
if((q_high==4'd0)&&(q_low==4'd0))
begin
q_low<=4'd7;
q_high<=4'd8;
end
end
default:
begin
q_low<=q_low;
q_high<=q_high;
end
endcase
end
else
begin
q_low<=q_low;
q_high<=q_high;
end
end
assignCup=(({S1,S0}==2'b10)&&((q_high==4'd0)&&(q_low==4'd0)));
assignCdown=(({S1,S0}==2'b01)&&((q_high==4'd8)&&(q_low==4'd7)));
endmodule
十二进制可逆计数器(没有数码管显示)
代码:
modulell2014111536_7(
inputclr,clk,load,en,updown,
input[3:
0]d,
outputco,
outputreg[3:
0]q);
assignco=en&(q==0);//whenq=0,co=1
always@(negedgeclkornegedgeclr)
begin
if(!
clr)q<=0;
elseif(!
load)q<=d;
elseif(!
en)while(!
en);//en=1,jishuen=0,baochi
else
begin
if(updown)
begin
if(q>=11)q<=0;
elseq<=q+1;
end
else
begin
if(q<=0)q<=11;
elseq<=q-1;
end
end
end
endmodule
电路图:
仿真波形:
实验8PWM分频器
代码:
modulell1536_8_1(clk,a,pwmont,temp);
inputclk;
input[3:
0]a;
outputregpwmont;
outputreg[3:
0]temp;
wire[3:
0]k;
assignk=a;
always@(posedgeclk)
begin
if(tempbegintemp<=temp+1;pwmont<=1;end
elseif(temp<9)
begintemp<=temp+1;pwmont<=0;end
elseif(temp==9)
begintemp<=0;pwmont<=0;end
elsetemp<=0;
end
endmodule
modulell1536_8_2(clk,cout,q1);
inputclk;
reg[15:
0]q1=0;
outputq1;
outputregcout;
always@(posedgeclk)
begin
q1=q1+1;
if(q1<=25000)
cout=1;
elseif(q1<50000)cout=0;
elseif(q1==50000)q1=0;
elsecout=0;
end
endmodule
原理图:
仿真波形: