数电实验.docx

1、数电实验实验2、3 quartus原理图设计原理图：仿真波形：实验4BCD码-七段译码器：module decode4_7(codeout,indec);input3:0 indec;output reg6:0 codeout;always(indec)begincase(indec)4d0:codeout=7b1111110;4d1:codeout=7b0110000;4d2:codeout=7b1101101;4d3:codeout=7b1111001;4d4:codeout=7b0110011;4d5:codeout=7b1011011;4d6:codeout=7b1011111;4d7

2、:codeout=7b1110000;4d8:codeout=7b1111111;4d9:codeout=7b1111011;default: codeout=7bx;endcaseendendmodule一位数值比较器：module FILE2(a_gt,a_eq,a_lt,a,b);input a,b;output a_gt,a_eq,a_lt;assign a_gt=a&b;assign a_eq=a&b|a&b;assign a_lt=a&b;endmodule电路图：仿真波形：比较器译码器：实验5集成触发器应用及彩灯控制器原理图：JK触发器：JKFF仿真波形：实验6 7位左移移位寄存

3、器原理图：仿真波形：实验7 88进制可逆计数器module ll1536(data,CP,CR,CNT_EN,S1,S0,q_low,q_high,Cup,Cdown);input CP,CR;input CNT_EN,S1,S0;input 7:0data;output reg 3:0q_low;output reg 3:0q_high;output wire Cup,Cdown;always(posedge CP or negedge CR)begin if(CR) begin q_low=4d0; q_high=4d0; end else if(CNT_EN) begin case(S1

4、,S0) 2b11: begin q_high,q_low=data; end 2b10: begin if(q_low4d9) q_low=q_low+1d1; else begin q_low=4d0; q_high=q_high+1d1; end if(q_high = 4d8) & (q_low = 4d7) begin q_low=4d0; q_high4d0) q_low=q_low-1d1; else begin q_low=4d9; q_high=q_high-1d1; end if(q_high = 4d0) & (q_low = 4d0) begin q_low=4d7;

5、q_high=4d8; end end default: begin q_low=q_low; q_high=q_high; end endcase end else begin q_low=q_low; q_high=q_high; endendassign Cup=(S1,S0 = 2b10) & (q_high = 4d0) & (q_low = 4d0);assign Cdown=(S1,S0 = 2b01) & (q_high = 4d8) & (q_low = 4d7);endmodule十二进制可逆计数器（没有数码管显示）代码：module ll2014111536_7( inp

6、ut clr, clk, load, en, updown, input3:0d, output co, output reg 3:0q); assign co=en&(q=0); /when q=0, co=1 always(negedge clk or negedge clr) begin if(!clr) q=0; else if(!load) q=11) q=0; else q=q+1; end else begin if(q=0) q=11; else q=q-1; end end endendmodule电路图：仿真波形：实验8 PWM 分频器代码：module ll1536_8_

7、1(clk,a,pwmont,temp);input clk;input 3:0a;output reg pwmont;output reg3:0temp;wire3:0k;assign k=a;always (posedge clk)beginif (tempk)begin temp=temp+1;pwmont=1;endelse if(temp9)begin temp=temp+1;pwmont=0;endelse if(temp=9)begin temp=0;pwmont=0;endelse temp=0;end endmodulemodule ll1536_8_2(clk,cout,q1);input clk;reg 15:0q1=0;output q1;output reg cout;always (posedge clk)begin q1=q1+1; if(q1=25000) cout=1; else if (q150000)cout=0; else if(q1=50000)q1=0; else cout=0; end endmodule原理图：仿真波形：