毕业设计英文翻译2.docx

毕业设计英文翻译2.docx

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毕业设计英文翻译2

英文资料

AT89C52internalstructureanalysis

Description

TheAT89S52isalow-power,high-performanceCMOS8-bitmicrocontrollerwith8Kbytesofin-systemprogrammableFlashmemory.ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindustry-standard80C51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithin-systemprogrammableFlashonamonolithicchip,theAtmelAT89S52isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.TheAT89S52providesthefollowingstandardfeatures:

8KbytesofFlash,256bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,three16-bittimer/counters,asix-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextinterruptorhardwarereset.

PinDescription

VCC

Supplyvoltage.

GND

Ground.

Port0

Port0isan8-bitopendrainbidirectionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.Port0canalsobeconfiguredtobethemultiplexedloworderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.

Port1

Port1isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseoftheinternalpullups.Inaddition,P1.0andP1.1canbeconfiguredtobethetimer/counter2externalcountinput（P1.0/T2）andthetimer/counter2triggerinput（P1.1/T2EX）,respectively,asshowninthefollowingtable.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.

Port2

Port2isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses（MOVX@DPTR）.Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses（MOVX@RI）,Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.

Port3

Port3isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseofthepullups.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S52,asshowninthefollowingtable.Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.

RST

Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.ThispindrivesHighfor96oscillatorperiodsaftertheWatchdogtimesout.TheDISRTObitinSFRAUXR（address8EH）canbeusedtodisablethisfeature.InthedefaultstateofbitDISRTO,theRESETHIGHoutfeatureisenabled.

ALE/PROG

AddressLatchEnable（ALE）isanoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput（PROG）duringFlashprogramming.Innormaloperation,ALEisemittedataconstantrateof1/6theoscillatorfrequencyandmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternaldatamemory.Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.

PSEN

ProgramStoreEnable（PSEN）isthereadstrobetoexternalprogrammemory.WhentheAT89S52isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.

EA/VPP

ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.EAshouldbestrappedtoVCCforinternalprogramexecutions.Thispinalsoreceivesthe12-voltprogrammingenablevoltage（VPP）duringFlashprogramming.

XTAL1

Inputtotheinvertingoscillatoramplifierandinputtothe

internalclockoperatingcircuit.

XTAL2

Outputfromtheinvertingoscillatoramplifier.

SpecialFunctionRegisters

Amapoftheon-chipmemoryareacalledtheSpecialFunctionRegister（SFR）spaceisshowninTable1.Notethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybeusedinfutureproductstoinvokenewfeatures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.

Timer2Registers:

ControlandstatusbitsarecontainedinregistersT2CON（showninTable2）andT2MOD（showninTable3）forTimer2.Theregisterpair（RCAP2H,RCAP2L）aretheCapture/ReloadregistersforTimer2in16-bitcapturemodeor16-bitauto-reloadmode.

InterruptRegisters:

TheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthesixinterruptsourcesintheIPregister.

MemoryOrganization

MCS-51deviceshaveaseparateaddressspaceforProgramandDataMemory.Upto64KbyteseachofexternalProgramandDataMemorycanbeaddressed.

ProgramMemory

IftheEApinisconnectedtoGND,allprogramfetchesaredirectedtoexternalmemory.OntheAT89S52,ifEAisconnectedtoVCC,programfetchestoaddresses0000Hthrough1FFFHaredirectedtointernalmemoryandfetchestoaddresses2000HthroughFFFFHaretoexternalmemory.

DataMemory

TheAT89S52implements256bytesofon-chipRAM.Theupper128bytesoccupyaparalleladdressspacetotheSpecialFunctionRegisters.Thismeansthattheupper128byteshavethesameaddressesastheSFRspacebutarephysicallyseparatefromSFRspace.Whenaninstructionaccessesaninternallocationaboveaddress7FH,theaddressmodeusedintheinstructionspecifieswhethertheCPUaccessestheupper128bytesofRAMortheSFRspace.InstructionswhichusedirectaddressingaccessoftheSFRspace.Forexample,thefollowingdirectaddressinginstructionaccessestheSFRatlocation0A0H（whichisP2）.MOV0A0H,#data

Instructionsthatuseindirectaddressingaccesstheupper128bytesofRAM.Forexample,thefollowingindirectaddressinginstruction,whereR0contains0A0H,accessesthedatabyteataddress0A0H,ratherthanP2（whoseaddressis0A0H）.

MOV@R0,#data

Notethatstackoperationsareexamplesofindirectaddressing,sotheupper128bytesofdataRAMareavailableasstackspace.

WatchdogTimer

（One-timeEnabledwithReset-out）

TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets.TheWDTconsistsofa13-bitcounterandtheWatchdogTimerReset（WDTRST）SFR.TheWDTisdefaultedtodisablefromexitingreset.ToenabletheWDT,ausermustwrite

01EHand0E1HinsequencetotheWDTRSTregister（SFRlocation0A6H）.WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.TheWDTtimeoutperiodisdependentontheexternalclockfrequency.ThereisnowaytodisabletheWDTexceptthroughreset（eitherhardwareresetorWDToverflowreset）.WhenWDToverflows,itwilldriveanoutputRESETHIGHpulseattheRSTpin.

UsingtheWDT

ToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister（SFRlocation0A6H）.WhentheWDTisenabled,theuserneedstoserviceitbywriting01EHand0E1HtoWDTRSTtoavoidaWDToverflow.The13-bitcounteroverflowswhenitreaches8191（1FFFH）,andthiswillresetthedevice.WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.ThismeanstheusermustresettheWDTatleastevery8191machinecycles.ToresettheWDTtheusermustwrite01EHand0E1HtoWDTRST.WDTRSTisawrite-onlyregister.TheWDTcountercannotbereadorwritten.WhenWDToverflows,itwillgenerateanoutputRESETpulseattheRSTpin.TheRESETpulsedurationis96xTOSC,whereTOSC=1/FOSC.Tomakethebest