Static Timing Analysis for Nanometer Designs_ A Practical Approach.pdf

Static Timing Analysis for Nanometer Designs_ A Practical Approach.pdf

《Static Timing Analysis for Nanometer Designs_ A Practical Approach.pdf》由会员分享，可在线阅读，更多相关《Static Timing Analysis for Nanometer Designs_ A Practical Approach.pdf（588页珍藏版）》请在冰豆网上搜索。

StaticTimingAnalysisforNanometerDesignsAPracticalApproachJ.BhaskerRakeshChadhaStaticTimingAnalysisforNanometerDesignsAPracticalApproachJ.BhaskerRakeshChadhaeSiliconCorporationeSiliconCorporationISBN978-0-387-93819-6e-ISBN978-0-387-93820-2LibraryofCongressControlNumber:

2009921502Allrightsreserved.Thisworkmaynotbetranslatedorcopiedinwholeorinpartwithoutthewrittenpermissionofthepublisher（SpringerScience+BusinessMedia,LLC,233SpringStreet,NewYork,NY10013,USA）,exceptforbriefexcerptsinconnectionwithreviewsorscholarlyanalysis.Useinconnectionwithanyformofinformationstorageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilarmethodologynowknownorhereafterdevelopedisforbidden.Theuseinthispublicationoftradenames,trademarks,servicemarksandsimilarterms,eveniftheyarenotidentifiedassuch,isnottobetakenasanexpressionofopinionastowhetherornottheyaresubjecttoproprietaryrights.Whiletheadviceandinformationinthisbookarebelievedtobetrueandaccurateatthedateofgoingtopress,neithertheauthorsnortheeditorsnorthepublishercanacceptanylegalresponsibilityforanyerrorsoromissionsthatmaybemade.Thepublishermakesnowarranty,expressorimplied,withrespecttothematerialcontainedherein.Somematerialreprintedfrom“IEEEStd.1497-2001,IEEEStandardforStandardDelayFormat（SDF）fortheElectronicDesignProcess;IEEEStd.1364-2001,IEEEStandardVerilogHardwareDescriptionLanguage;IEEEStd.1481-1999,IEEEStandardforIntegratedCircuit（IC）DelayandPowerCalculationSystem”,withpermissionfromIEEE.TheIEEEdisclaimsanyresponsibilityorliabilityresultingfromtheplacementanduseinthedescribedmanner.LibertyformatspecificationandSDCformatspecificationdescribedinthistextarecopyrightSynopsysInc.andarereprintedaspertheSynopsysopen-sourcelicenseagreement.TimingreportsarereportedusingPrimeTimewhicharecopyrightSynopsys,Inc.Usedwithpermission.Synopsys&PrimeTimeareregisteredtrademarksofSynopsys,Inc.AppendicesonSDFandSPEFhavebeenreprintedfrom“TheExchangeFormatHandbook”withpermissionfromStarGalaxyPublishing.Printedonacid-freeSpringerScience+BusinessMedia,LLC2009DOI:

10.1007/978-0-387-93820-2Suite615Allentown,PA18103,USA890MountainAve1605N.CedarCrestBlvd.NewProvidence,NJ07974,USAvContentsPreface.xvCHAPTER1:

Introduction.11.1NanometerDesigns.11.2WhatisStaticTimingAnalysis?

.21.3WhyStaticTimingAnalysis?

.4CrosstalkandNoise,41.4DesignFlow.51.4.1CMOSDigitalDesigns.51.4.2FPGADesigns.81.4.3AsynchronousDesigns.81.5STAatDifferentDesignPhases.91.6LimitationsofStaticTimingAnalysis.91.7PowerConsiderations.121.8ReliabilityConsiderations.131.9OutlineoftheBook.13CHAPTER2:

STAConcepts.152.1CMOSLogicDesign.152.1.1BasicMOSStructure.152.1.2CMOSLogicGate.162.1.3StandardCells.182.2ModelingofCMOSCells.202.3SwitchingWaveform.23CONTENTSvi2.4PropagationDelay.252.5SlewofaWaveform.282.6SkewbetweenSignals.302.7TimingArcsandUnateness.332.8MinandMaxTimingPaths.342.9ClockDomains.362.10OperatingConditions.39CHAPTER3:

StandardCellLibrary.433.1PinCapacitance.443.2TimingModeling.443.2.1LinearTimingModel.463.2.2Non-LinearDelayModel.47ExampleofNon-LinearDelayModelLookup,523.2.3ThresholdSpecificationsandSlewDerating.533.3TimingModels-CombinationalCells.563.3.1DelayandSlewModels.57PositiveorNegativeUnate,583.3.2GeneralCombinationalBlock.593.4TimingModels-SequentialCells.603.4.1SynchronousChecks:

SetupandHold.62ExampleofSetupandHoldChecks,62NegativeValuesinSetupandHoldChecks,643.4.2AsynchronousChecks.66RecoveryandRemovalChecks,66PulseWidthChecks,66ExampleofRecovery,RemovalandPulseWidthChecks,673.4.3PropagationDelay.683.5State-DependentModels.70XOR,XNORandSequentialCells,703.6InterfaceTimingModelforaBlackBox.733.7AdvancedTimingModeling.753.7.1ReceiverPinCapacitance.76SpecifyingCapacitanceatthePinLevel,77SpecifyingCapacitanceattheTimingArcLevel,773.7.2OutputCurrent.79CONTENTSvii3.7.3ModelsforCrosstalkNoiseAnalysis.80DCCurrent,82OutputVoltage,83PropagatedNoise,83NoiseModelsforTwo-StageCells,84NoiseModelsforMulti-stageandSequentialCells,853.7.4OtherNoiseModels.873.8PowerDissipationModeling.883.8.1ActivePower.88DoubleCountingClockPinPower?

923.8.2LeakagePower.923.9OtherAttributesinCellLibrary.94AreaSpecification,94FunctionSpecification,95SDFCondition,953.10CharacterizationandOperatingConditions.96WhatistheProcessVariable?

963.10.1DeratingusingK-factors.973.10.2LibraryUnits.99CHAPTER4:

InterconnectParasitics.1014.1RLCforInterconnect.102T-model,103Pi-model,1044.2WireloadModels.1054.2.1InterconnectTrees.1084.2.2SpecifyingWireloadModels.1104.3RepresentationofExtractedParasitics.1134.3.1DetailedStandardParasiticFormat.1134.3.2ReducedStandardParasiticFormat.1154.3.3StandardParasiticExchangeFormat.1174.4RepresentingCouplingCapacitances.1184.5HierarchicalMethodology.119BlockReplicatedinLayout,1204.6ReducingParasiticsforCriticalNets.120ReducingInterconnectResistance,120IncreasingWireSpacing,121CONTENTSviiiParasiticsforCorrelatedNets,121CHAPTER5:

DelayCalculation.1235.1Overview.1235.1.1DelayCalculationBasics.1235.1.2DelayCalculationwithInterconnect.125Pre-layoutTiming,125Post-layoutTiming,1265.2CellDelayusingEffectiveCapacitance.1265.3InterconnectDelay.131ElmoreDelay,132HigherOrderInterconnectDelayEstimation,134FullChipDelayCalculation,1355.4SlewMerging.1355.5DifferentSlewThresholds.1375.6DifferentVoltageDomains.1405.7PathDelayCalculation.1405.7.1CombinationalPathDelay.1415.7.2PathtoaFlip-flop.143InputtoFlip-flopPath,143Flip-floptoFlip-flopPath,1445.7.3MultiplePaths.1455.8SlackCalculation.146CHAPTER6:

CrosstalkandNoise.1476.1Overview.1486.2CrosstalkGlitchAnalysis.1506.2.1Basics.1506.2.2TypesofGlitches.152RiseandFallGlitches,152OvershootandUndershootGlitches,1526.2.3GlitchThresholdsandPropagation.153DCThresholds,153ACThresholds,1566.2.4NoiseAccumulationwithMultipleAggressors.1606.2.5AggressorTimingCorrelation.160CONTENTSix6.2.6AggressorFunctionalCorrelation.1626.3CrosstalkDelayAnalysis.1646.3.1Basics.1646.3.2PositiveandNegativeCrosstalk.1676.3.3AccumulationwithMultipleAggressors.1696.3.4AggressorVictimTimingCorrelation.1696.3.5AggressorVictimFunctionalCorrelation.1716.4TimingVerificationUsingCrosstalkDelay.1716.4.1SetupAnalysis.1726.4.2HoldAnalysis.1736.5ComputationalComplexity.175HierarchicalDesignandAnalysis,175FilteringofCouplingCapacitances,1756.6NoiseAvoidanceTechniques.176CHAPTER7:

ConfiguringtheSTAEnvironment.1797.1WhatistheSTAEnvironment?

.1807.2SpecifyingClocks.1817.2.1ClockUncertainty.1867.2.2ClockLatency.1887.3GeneratedClocks.190ExampleofMasterClockatClockGatingCellOutput,194GeneratedClockusingEdgeandEdge_shiftOptions,195GeneratedClockusingInvertOption,198ClockLatencyforGeneratedClocks,200TypicalClockGenerationScenario,2007.4ConstrainingInputPaths.2017.5ConstrainingOutputPaths.205ExampleA,205ExampleB,206ExampleC,2067.6TimingPathGroups.2077.7ModelingofExternalAttributes.2107.7.1ModelingDriveStrengths.2117.7.2ModelingCapacitiveLoad.2147.8DesignRuleChecks.215CONTENTSx7.9VirtualClocks.2177.10RefiningtheTimingAnalysis.2197.10.1SpecifyingInactiveSignals.2207.10.2BreakingTimingArcsinCells.2217.11Point-to-PointSpecification.2227.12PathSegmentation.224CHAPTER8:

TimingVerification.2278.1SetupTimingCheck.2288.1.1Flip-floptoFlip-flopPath.2318.1.2InputtoFlip-flopPath.237InputPathwithActualClock,2408.1.3Flip-floptoOutputPath.2428.1.4InputtoOutputPath.2448.1.5FrequencyHistogram.2468.2HoldTimingCheck.2488.2.1Flip-floptoFlip-flopPath.252HoldSlackCalculation,2538.2.2InputtoFlip-flopPath.2548.2.3Flip-floptoOutputPath.256Flip-floptoOutputPathwithActualClock,2578.2.4InputtoOutputPath.2598.3MulticyclePaths.260CrossingClockDomains,2668.4FalsePaths.2728.5Half-CyclePaths.2748.6RemovalTimingCheck.2778.7RecoveryTimingCheck.2798.8TimingacrossClockDomains.2818.8.1SlowtoFastClockDomains.2818.8.2FasttoSlowClockDomains.2898.9Examples.295Half-cyclePath-Case1,296Half-cyclePath-Case2,298FasttoSlowClockDomain,301SlowtoFastClockDomain,303CONTENTSxi8.10MultipleClocks.3058.10.1IntegerMultiples.3058.10.2Non-IntegerMultiples.3088.10.3PhaseShifted.314CHAPTER9:

InterfaceAnalysis.3179.1IOInterfaces.3179.1.1InputInterface.318WaveformSpecificationatInputs,318PathDelaySpecificationtoInputs,3219.1.2OutputInterface.323OutputWaveformSpecification,323ExternalPathDelaysforOutput,3279.1.3OutputChangewithinWindow.3289.2SRAMInterface.3369.3DDRSDRAMInterface.3419.3.1ReadCycle.3439.3.2WriteCycle.348Case1:

Internal2xClock,349Case2:

Internal1xClock,3549.4InterfacetoaVideoDAC.360CHAPTER10:

RobustVerification.36510.1On-ChipVariations.365AnalysiswithOCVatWorstPVTCondition,371OCVforHoldChecks,37310.2TimeBorrowing.377ExamplewithNoTimeBorrowed,379ExamplewithTimeBorrowed,382ExamplewithTimingViolation,38410.3DatatoDataChecks.38510.4Non-SequentialChecks.39210.5ClockGatingChecks.394Active-HighClockGating,396Active-LowClockGating,403ClockGatingwithaMultiplexer,406CONTENTSxiiClockGatingwithClockInversion,40910.6PowerManagement.41210.6.1ClockGating.41310.6.2PowerGating.41410.6.3MultiVtCells.416HighPerformanceBlockwithHighActivity,416HighPerformanceBlockwithLowActivity,41710.6.4WellBias.41710.7Backannotation.41810.7.1SPEF.41810.7.2SDF.41810.8Sign-offMethodology.418ParasiticInterconnectCorners,419OperatingModes,420PVTCorners,420Multi-ModeMulti-CornerAnalysis,42110.9StatisticalStaticTimingAnalysis.42210.9.1ProcessandInterconnectVariations.423GlobalProcessVari