Static Timing Analysis for Nanometer Designs_ A Practical Approach.pdf

1、 Static Timing Analysis for Nanometer Designs A Practical Approach J.Bhasker Rakesh Chadha Static Timing Analysis for Nanometer Designs A Practical Approach J.Bhasker Rakesh Chadha eSilicon Corporation eSilicon Corporation ISBN 978-0-387-93819-6 e-ISBN 978-0-387-93820-2 Library of Congress Control N

2、umber:2009921502 All rights reserved.This work may not be translated or copied in whole or in part without the written permission of the publisher(Springer Science+Business Media,LLC,233 Spring Street,New York,NY 10013,USA),except for brief excerpts in connection with reviews or scholarly analysis.U

3、se in connection with any form of information storage and retrieval,electronic adaptation,computer software,or by similar or dissimilar methodology now known or hereafter developed is forbidden.The use in this publication of trade names,trademarks,service marks and similar terms,even if they are not

4、 identified as such,is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights.While the advice and information in this book are believed to be true and accurate at the date of going to press,neither the authors nor the editors nor the publisher can ac

5、cept any legal responsibility for any errors or omissions that may be made.The publisher makes no warranty,express or implied,with respect to the material contained herein.Some material reprinted from“IEEE Std.1497-2001,IEEE Standard for Standard Delay Format(SDF)for the Electronic Design Process;IE

6、EE Std.1364-2001,IEEE Standard Verilog Hardware Description Language;IEEE Std.1481-1999,IEEE Standard for Integrated Circuit(IC)Delay and Power Calculation System”,with permission from IEEE.The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manne

7、r.Liberty format specification and SDC format specification described in this text are copyright Synopsys Inc.and are reprinted as per the Synopsys open-source license agreement.Timing reports are reported using PrimeTime which are copyright Synopsys,Inc.Used with permission.Synopsys&PrimeTime are r

8、egistered trademarks of Synopsys,Inc.Appendices on SDF and SPEF have been reprinted from“The Exchange Format Handbook”with permission from Star Galaxy Publishing.Printed on acid-free Springer Science+Business Media,LLC 2009 DOI:10.1007/978-0-387-93820-2 Suite 615Allentown,PA 18103,USA 890 Mountain A

9、ve1605 N.Cedar Crest Blvd.New Providence,NJ 07974,USA vContentsPreface.xvCHAPTER1:Introduction.11.1Nanometer Designs.11.2What is Static Timing Analysis?.21.3Why Static Timing Analysis?.4Crosstalk and Noise,41.4Design Flow.51.4.1CMOS Digital Designs.51.4.2FPGA Designs.81.4.3Asynchronous Designs.81.5S

10、TA at Different Design Phases.91.6Limitations of Static Timing Analysis.91.7Power Considerations.121.8Reliability Considerations.131.9Outline of the Book.13CHAPTER2:STA Concepts.152.1CMOS Logic Design.152.1.1Basic MOS Structure.152.1.2CMOS Logic Gate.162.1.3Standard Cells.182.2Modeling of CMOS Cells

11、.202.3Switching Waveform.23CONTENTSvi2.4Propagation Delay.252.5Slew of a Waveform.282.6Skew between Signals.302.7Timing Arcs and Unateness.332.8Min and Max Timing Paths.342.9Clock Domains.362.10Operating Conditions.39CHAPTER3:Standard Cell Library.433.1Pin Capacitance.443.2Timing Modeling.443.2.1Lin

12、ear Timing Model.463.2.2Non-Linear Delay Model.47Example of Non-Linear Delay Model Lookup,523.2.3Threshold Specifications and Slew Derating.533.3Timing Models-Combinational Cells.563.3.1Delay and Slew Models.57Positive or Negative Unate,583.3.2General Combinational Block.593.4Timing Models-Sequentia

13、l Cells.603.4.1Synchronous Checks:Setup and Hold.62Example of Setup and Hold Checks,62Negative Values in Setup and Hold Checks,643.4.2Asynchronous Checks.66Recovery and Removal Checks,66Pulse Width Checks,66Example of Recovery,Removal and Pulse Width Checks,673.4.3Propagation Delay.683.5State-Depend

14、ent Models.70XOR,XNOR and Sequential Cells,703.6Interface Timing Model for a Black Box.733.7Advanced Timing Modeling.753.7.1Receiver Pin Capacitance.76Specifying Capacitance at the Pin Level,77Specifying Capacitance at the Timing Arc Level,773.7.2Output Current.79CONTENTSvii3.7.3Models for Crosstalk

15、 Noise Analysis.80DC Current,82Output Voltage,83Propagated Noise,83Noise Models for Two-Stage Cells,84Noise Models for Multi-stage and Sequential Cells,853.7.4Other Noise Models.873.8Power Dissipation Modeling.883.8.1Active Power.88Double Counting Clock Pin Power?,923.8.2Leakage Power.923.9Other Att

16、ributes in Cell Library.94Area Specification,94Function Specification,95SDF Condition,953.10Characterization and Operating Conditions.96What is the Process Variable?,963.10.1Derating using K-factors.973.10.2Library Units.99CHAPTER4:Interconnect Parasitics.1014.1RLC for Interconnect.102T-model,103Pi-

17、model,1044.2Wireload Models.1054.2.1Interconnect Trees.1084.2.2Specifying Wireload Models.1104.3Representation of Extracted Parasitics.1134.3.1Detailed Standard Parasitic Format.1134.3.2Reduced Standard Parasitic Format.1154.3.3Standard Parasitic Exchange Format.1174.4Representing Coupling Capacitan

18、ces.1184.5Hierarchical Methodology.119Block Replicated in Layout,1204.6Reducing Parasitics for Critical Nets.120Reducing Interconnect Resistance,120Increasing Wire Spacing,121CONTENTSviiiParasitics for Correlated Nets,121CHAPTER5:Delay Calculation.1235.1Overview.1235.1.1Delay Calculation Basics.1235

19、.1.2Delay Calculation with Interconnect.125Pre-layout Timing,125Post-layout Timing,1265.2Cell Delay using Effective Capacitance.1265.3Interconnect Delay.131Elmore Delay,132Higher Order Interconnect Delay Estimation,134Full Chip Delay Calculation,1355.4Slew Merging.1355.5Different Slew Thresholds.137

20、5.6Different Voltage Domains.1405.7Path Delay Calculation.1405.7.1Combinational Path Delay.1415.7.2Path to a Flip-flop.143Input to Flip-flop Path,143Flip-flop to Flip-flop Path,1445.7.3Multiple Paths.1455.8Slack Calculation.146CHAPTER6:Crosstalk and Noise.1476.1Overview.1486.2Crosstalk Glitch Analys

21、is.1506.2.1Basics.1506.2.2Types of Glitches.152Rise and Fall Glitches,152Overshoot and Undershoot Glitches,1526.2.3Glitch Thresholds and Propagation.153DC Thresholds,153AC Thresholds,1566.2.4Noise Accumulation with Multiple Aggressors.1606.2.5Aggressor Timing Correlation.160CONTENTSix6.2.6Aggressor

22、Functional Correlation.1626.3Crosstalk Delay Analysis.1646.3.1Basics.1646.3.2Positive and Negative Crosstalk.1676.3.3Accumulation with Multiple Aggressors.1696.3.4Aggressor Victim Timing Correlation.1696.3.5Aggressor Victim Functional Correlation.1716.4Timing Verification Using Crosstalk Delay.1716.

23、4.1Setup Analysis.1726.4.2Hold Analysis.1736.5Computational Complexity.175Hierarchical Design and Analysis,175Filtering of Coupling Capacitances,1756.6Noise Avoidance Techniques.176CHAPTER7:Configuring the STA Environment.1797.1What is the STA Environment?.1807.2Specifying Clocks.1817.2.1Clock Uncer

24、tainty.1867.2.2Clock Latency.1887.3Generated Clocks.190Example of Master Clock at Clock Gating Cell Output,194Generated Clock using Edge and Edge_shift Options,195Generated Clock using Invert Option,198Clock Latency for Generated Clocks,200Typical Clock Generation Scenario,2007.4Constraining Input P

25、aths.2017.5Constraining Output Paths.205Example A,205Example B,206Example C,2067.6Timing Path Groups.2077.7Modeling of External Attributes.2107.7.1Modeling Drive Strengths.2117.7.2Modeling Capacitive Load.2147.8Design Rule Checks.215CONTENTSx7.9Virtual Clocks.2177.10Refining the Timing Analysis.2197

26、.10.1Specifying Inactive Signals.2207.10.2Breaking Timing Arcs in Cells.2217.11Point-to-Point Specification.2227.12Path Segmentation.224CHAPTER8:Timing Verification.2278.1Setup Timing Check.2288.1.1Flip-flop to Flip-flop Path.2318.1.2Input to Flip-flop Path.237Input Path with Actual Clock,2408.1.3Fl

27、ip-flop to Output Path.2428.1.4Input to Output Path.2448.1.5Frequency Histogram.2468.2Hold Timing Check.2488.2.1Flip-flop to Flip-flop Path.252Hold Slack Calculation,2538.2.2Input to Flip-flop Path.2548.2.3Flip-flop to Output Path.256Flip-flop to Output Path with Actual Clock,2578.2.4Input to Output

28、 Path.2598.3Multicycle Paths.260Crossing Clock Domains,2668.4False Paths.2728.5Half-Cycle Paths.2748.6Removal Timing Check.2778.7Recovery Timing Check.2798.8Timing across Clock Domains.2818.8.1Slow to Fast Clock Domains.2818.8.2Fast to Slow Clock Domains.2898.9Examples.295Half-cycle Path-Case 1,296H

29、alf-cycle Path-Case 2,298Fast to Slow Clock Domain,301Slow to Fast Clock Domain,303CONTENTSxi8.10Multiple Clocks.3058.10.1Integer Multiples.3058.10.2Non-Integer Multiples.3088.10.3Phase Shifted.314CHAPTER9:Interface Analysis.3179.1IO Interfaces.3179.1.1Input Interface.318Waveform Specification at In

30、puts,318Path Delay Specification to Inputs,3219.1.2Output Interface.323Output Waveform Specification,323External Path Delays for Output,3279.1.3Output Change within Window.3289.2SRAM Interface.3369.3DDR SDRAM Interface.3419.3.1Read Cycle.3439.3.2Write Cycle.348Case 1:Internal 2x Clock,349Case 2:Inte

31、rnal 1x Clock,3549.4Interface to a Video DAC.360CHAPTER10:Robust Verification.36510.1On-Chip Variations.365Analysis with OCV at Worst PVT Condition,371OCV for Hold Checks,37310.2Time Borrowing.377Example with No Time Borrowed,379Example with Time Borrowed,382Example with Timing Violation,38410.3Data

32、 to Data Checks.38510.4Non-Sequential Checks.39210.5Clock Gating Checks.394Active-High Clock Gating,396Active-Low Clock Gating,403Clock Gating with a Multiplexer,406CONTENTSxiiClock Gating with Clock Inversion,40910.6Power Management.41210.6.1Clock Gating.41310.6.2Power Gating.41410.6.3Multi Vt Cell

33、s.416High Performance Block with High Activity,416High Performance Block with Low Activity,41710.6.4Well Bias.41710.7Backannotation.41810.7.1SPEF.41810.7.2SDF.41810.8Sign-off Methodology.418Parasitic Interconnect Corners,419Operating Modes,420PVT Corners,420Multi-Mode Multi-Corner Analysis,42110.9Statistical Static Timing Analysis.42210.9.1Process and Interconnect Variations.423Global Process Vari