Synopsys Powergating Design Methodology based on SMIC 90nm Process.docx

Synopsys Powergating Design Methodology based on SMIC 90nm Process.docx

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SynopsysPowergatingDesignMethodologybasedonSMIC90nmProcess

SynopsysPower-gatingDesignMethodologybasedonSMIC90nmProcess

EugeneWang

SemiconductorManufacturingInternationalCorporation（SMIC）

Abstract

Powerconsumptionhasalwaysbeenabigissueforportableapplication.Intoday’srapidgrowingtechnologyworld,multi-mediaanddiversifiedfunctionswereincorporatedintoportabledeviceshavemadepowerconsumptionafurtherchallenge.Eitherbattery’slifetimehastobeprolongedorarchitectureofthedesignneedstoberemodeled.Thispaper,however,willfocusonimplementationoflowpowerdesignwithSynopsyslowpowersolution.Itwillhighlightleakagepowerreductionthroughpower-gatingtechnique.ThesuggestedmethodhasbeenachievedbasedonARM’slibraryforSMIC（SemiconductorManufacturingInternationalCorporation）90nmprocess.Thispaperfirstillustratesleakagecontroltheory.Then,itexplorestheconceptofpower-gating.Finally,itdiscussedadvancedpower-gatingdesignmethodologyfromRTLtoverifiedGDSII.ThispaperiswrittenbasedonSMIC-SynopsysReferenceFlow3.2anchoredbySynopsysGalaxyimplementationplatformandDiscoveryverificationplatform.

Keywords:

90nm,leakagepower,power-gating,ReferenceFlow,SMIC,Synopsys

1.0Introduction

Asweenteredintodeepsub-micronprocess,downscalingofgeometrysizemadecurrentdensitysubstantial.Powerdissipationraises.Designerstendtolowersupplyvoltagetoreducetheoverallpowerconsumptionandyet,thisleadstoperformanceweakening.Byutilizinglowthresholdvoltage（Vth）devices,designersareabletoalleviateperformancedegradationbutattheexpenseofleakagepower.Thisshowsthatthereisneverawin-winsolutioninsemiconductorfield.Thesolutiontothisproblemmaybecometheproblemofthenext.Designersareoftenfacingproblemstobalancetradeoffsbetweendifferentdesignaspects.Uptoafewyearsback,leakagepowerwasstilltolerable.Nowithasturnedintoasignificantfactorthatcannotbeneglected.Infact,leakagepowerincreasesexponentiallyastechnologyscalesdownward.ThispaperwilluseARMlibraryforSMIC90nmprocesstodemonstratehowleakagepowercanbehandledduringdesignflowfromRTLtoGDSII.

2.0LeakageCurrentControlTheory

Leakagepowerariseswheneverthereisleakagecurrentflowduringstandbymode.InCMOS（ComplementaryMetal-OxideSemiconductor）technology,leakagecurrenthasmanydifferentcomponents.Yet,thebiggestportioncomesfromsub-thresholdleakagecurrent.Sub-thresholdleakagecurrentis,infact,drain-to-sourcecurrentflowsinthechannelofaMOSdeviceintheweakinversionregioninwhichthediffusioncurrentiscausedbytheminoritycarriers.Forexample,whenalowinputvoltageisappliedtoaninverter,ahighvoltagepotentialisobservedatitsoutputterminal.Intheory,PMOSisswitchedonandNMOSisswitchedoff.Inreality,NMOSisnotcompletelyshut-off;thereisstillaleakagecurrentflowinginitschannelduetotheVDDpotentialofVDS.Thisleakagecurrentcanbeexpressedbythefollowingequation[1].

whereIDSisthedraintosourcecurrent;VDSisthedraintosourcevoltage;VTisthethresholdvoltage;VGSisthetransistorgatetosourcevoltage;Kandnarefunctionsoftechnology,andηisthedrain-inducedbarrierlowering（DIBL）coefficient.VTplaysanimportantroleinthisequation.TheincreaseofVTmeansthereductionofleakagecurrentexponentially.However,theincreaseofthresholdvoltagealsomeansthedelayofswitchingonandoffofMOSdevice.Tosomeextent,thistechniqueisstillfeasibleintheCMOStechnology.Nevertheless,ifonetakesacloserlookattheaboveequation,onecanalsoreduceleakagecurrentbyloweringVGS（transistorgatetosourcevoltage）.Aclearpictureisshownbelowbyplottingtheaboveequation,assumingaconstantdraintosourcevoltageandzerobodytosourcevoltage[1].

Thisgraphshowsthatgatetosourcevoltageincreasesexponentiallywithdraincurrent.Asaresult,decreasingthetransistorgatetosourcevoltagewillgreatlyreducetheleakagecurrentandhenceleakagepower.Thisistheprinciplethatthepaperisbasedontodiscusstheconceptofpower-gatinginthenextchapter.

3.0ConceptofPower-gating

Figure1.Fine-grainpower-gatingwithinverter

Power-gatingreducesleakagebyreducingtransistorgatetosourcevoltage.Theoperationofpower-gatingtechniqueissimple.Aheader（p-typetransistor）switchisplacedinbetweenablockandpowertocontrolsupplypowerfromthisblockwithsleepsignal（PleaserefertoFigure1）.Inactivemode,virtualvoltage（VVDD）isactingaspowersupplyatapotentialofapproximatelyVDDtotheblock;leakagepowerexistsbothinheaderandthiscircuitblock.Instandbymode,headerisswitchedoff,meaningthatvirtualvoltageisbeginningtodropwithtime.