Synopsys Powergating Design Methodology based on SMIC 90nm Process.docx

1、Synopsys Powergating Design Methodology based on SMIC 90nm ProcessSynopsys Power-gating Design Methodology based on SMIC 90nm ProcessEugene WangSemiconductor Manufacturing International Corporation (SMIC)AbstractPower consumption has always been a big issue for portable application. In todays rapid

2、growing technology world, multi-media and diversified functions were incorporated into portable devices have made power consumption a further challenge. Either batterys lifetime has to be prolonged or architecture of the design needs to be remodeled. This paper, however, will focus on implementation

3、 of low power design with Synopsys low power solution. It will highlight leakage power reduction through power-gating technique. The suggested method has been achieved based on ARMs library for SMIC (Semiconductor Manufacturing International Corporation) 90nm process. This paper first illustrates le

4、akage control theory. Then, it explores the concept of power-gating. Finally, it discussed advanced power-gating design methodology from RTL to verified GDSII. This paper is written based on SMIC-Synopsys Reference Flow 3.2 anchored by Synopsys Galaxy implementation platform and Discovery verificati

5、on platform.Keywords: 90nm, leakage power, power-gating, Reference Flow, SMIC, Synopsys1.0 IntroductionAs we entered into deep sub-micron process, down scaling of geometry size made current density substantial. Power dissipation raises. Designers tend to lower supply voltage to reduce the overall po

6、wer consumption and yet, this leads to performance weakening. By utilizing low threshold voltage (Vth) devices, designers are able to alleviate performance degradation but at the expense of leakage power. This shows that there is never a win-win solution in semiconductor field. The solution to this

7、problem may become the problem of the next. Designers are often facing problems to balance tradeoffs between different design aspects. Up to a few years back, leakage power was still tolerable. Now it has turned into a significant factor that cannot be neglected. In fact, leakage power increases exp

8、onentially as technology scales downward. This paper will use ARM library for SMIC 90nm process to demonstrate how leakage power can be handled during design flow from RTL to GDSII.2.0 Leakage Current Control TheoryLeakage power arises whenever there is leakage current flow during standby mode. In C

9、MOS (Complementary Metal-Oxide Semiconductor) technology, leakage current has many different components. Yet, the biggest portion comes from sub-threshold leakage current. Sub-threshold leakage current is, in fact, drain-to-source current flows in the channel of a MOS device in the weak inversion re

10、gion in which the diffusion current is caused by the minority carriers. For example, when a low input voltage is applied to an inverter, a high voltage potential is observed at its output terminal. In theory, PMOS is switched on and NMOS is switched off. In reality, NMOS is not completely shut-off;

11、there is still a leakage current flowing in its channel due to the VDD potential of VDS. This leakage current can be expressed by the following equation 1.where IDS is the drain to source current; VDS is the drain to source voltage; VT is the threshold voltage; VGS is the transistor gate to source v

12、oltage; K and n are functions of technology, andis the drain-induced barrier lowering (DIBL) coefficient. VT plays an important role in this equation. The increase of VT means the reduction of leakage current exponentially. However, the increase of threshold voltage also means the delay of switching

13、 on and off of MOS device. To some extent, this technique is still feasible in the CMOS technology. Nevertheless, if one takes a closer look at the above equation, one can also reduce leakage current by lowering VGS (transistor gate to source voltage). A clear picture is shown below by plotting the

14、above equation, assuming a constant drain to source voltage and zero body to source voltage 1.This graph shows that gate to source voltage increases exponentially with drain current. As a result, decreasing the transistor gate to source voltage will greatly reduce the leakage current and hence leaka

15、ge power. This is the principle that the paper is based on to discuss the concept of power-gating in the next chapter.3.0 Concept of Power-gatingFigure 1. Fine-grain power-gating with inverterPower-gating reduces leakage by reducing transistor gate to source voltage. The operation of power-gating te

16、chnique is simple. A header (p-type transistor) switch is placed in between a block and power to control supply power from this block with sleep signal (Please refer to Figure 1). In active mode, virtual voltage (VVDD) is acting as power supply at a potential of approximately VDD to the block; leakage power exists both in header and this circuit block. In standby mode, header is switched off, meaning that virtual voltage is beginning to drop with time.