EDA考试模块Word文档格式.docx

EDA考试模块Word文档格式.docx

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"

10"

001"

010"

01"

011"

100"

101"

110"

11"

whenothers;

=Y

（1）;

=Y（0）;

--full_adder3

whenABC="

else

;

--full_adder4

process（ABC,Ai,Bi,Ci_1）

IfABC="

thenY<

;

elsifABC="

elseY<

endif;

endprocess;

--full_adder5

caseABCis

when"

=>

111"

endcase;

D锁存器

entitydff1is

port（D,clk:

Q:

bufferstd_logic）;

enddff1;

architecturebehaveofdff1is

process（clk,Q）

begin

ifclk'

eventandclk='

1'

thenQ<

=D;

endif;

endprocess;

endbehave;

JK触发器

useieee.std_logic_arith.all;

useieee.std_logic_unsigned.all;

entityJK_chufais

Port（sd,rd,j,k,clk:

instd_logic;

q,qb:

outstd_logic

）;

endJK_chufa;

architecturebehaveofJK_chufais

signalqn:

std_logic;

process（clk）

ifsd='

0'

andrd='

thenqn<

='

elsifsd='

then

ifrising_edge（clk）then

qn<

=（jandnotqn）or（notkandqn）;

q<

=qn;

qb<

=notqn;

10进制计数器

entitymodule_10is

port（ep,et,clr,load,clk:

d:

instd_logic_vector（3downto0）;

co:

outstd_logic;

q:

bufferstd_logic_vector（3downto0）

endmodule_10;

architecturebehaveofmodule_10is

co<

when（q="

1001"

andep='

andet='

）else

'

process（clk,clr）

if（clr='

）thenq<

0000"

elsifrising_edge（clk）then

ifload='

thenq<

=d;

elsif（ep='

）then

if（q=9）thenq<

elseq<

=q+1;

扫描显示

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

USEIEEE.STD_LOGIC_ARITH.ALL;

ENTITYCNT8IS

PORT（CLK:

INSTD_LOGIC;

BUFFERSTD_LOGIC_VECTOR（2DOWNTO0））;

END;

ARCHITECTUREBEHOFCNT8IS

BEGIN

PROCESS（CLK）

IFRISING_EDGE（CLK）THEN

IFQ=7THENQ<

ELSEQ<

=Q+1;

ENDIF;

ENDPROCESS;

entitydec7sis

port（a:

instd_logic_vector（2downto0）;

led7s:

outstd_logic_vector（6downto0））;

enddec7s;

architecturebehaveofdec7sis

begin

process（a）

begin

caseais

=>

led7s<

1111111"

1110000"

1011111"

--abcdefg

1011011"

0110011"

1111001"

1101101"

0110000"

whenothers=>

null;

endcase;

endbehave;

entitydivxsis

port（clk20m:

clk1:

enddivxs;

architecturebhvofdivxsis

signalcount:

std_logic_vector（24downto0）;

process（clk20m）

ifrising_edge（clk20m）then

ifcount=1000then

count<

=（others=>

'

）;

elsecount<

=count+1;

ifcount<

500then

clk1<

elseclk1<

endbhv;

交通灯

entitydiv_wxis

enddiv_wx;

architecturebhvofdiv_wxis

ifcount=5000then

2500then

entityseg7decis

port（din:

instd_logic_vector（3downto0）;

segout:

endseg7dec;

architecturebehaveofseg7decis

process（din）

casedinis

when"

segout<

0111111"

0001"

0000110"

0010"

0011"

1001111"

0100"

1100110"

0101"

0110"

1111101"

0111"

0000111"

1000"

1101111"

whenothers=>

null;

endcase;

entitydivis

enddiv;

architecturebhvofdivis

ifcount=10000000then

5000000then

entitytraffic_controlis

port（clk1hz,rst,clk_20mhz:

--col:

outstd_logic;

--coh:

outstd_logic_vector（1downto0）;

counter:

outstd_logic_vector（3downto0）;

outstd_logic_vector（11downto0））;

endtraffic_control;

architecturebhvoftraffic_controlis

typestate_valueis（s1,s2,s3,s4）;

signalstate:

state_value;

signalcounterh:

std_logic_vector（3downto0）;

signalcounterl:

p1:

process（rst,clk1hz,clk_20mhz）

ifrst='

state<

=s1;

counterh<

counterl<

100001100001"

elsifrising_edge（clk1hz）then

casestateis

whens1=>

ifcounterh="

andcounterl="

state<

=s2;

q<

010001010001"

counterh<

counterl<

elsestate<

ifcounterl="

thencounterh<

=counterh-1;

counterl<

elsecounterl<

=counterl-1;

endif;

endif;

whens2=>

state<

=s3;

q<

001100001100"

counterh<

counterl<

elsestate<

ifcounterl="

elsecounterl<

endif;

endif;

whens3=>

=s4;

010100010100"

elsestate<

whens4=>

elsestate<

ifcounterl="

elsecounterl<

endif;

whenothers=>

NULL;

ifclk_20mhz='

thencounter<

=counterh;

elsecounter<

=counterl;

endprocessp1;

endbhv;

数字钟

entitycounter_60is

port（en,rest,clk_1hz:

--d:

instd_logic_vector（7downto0）;

qh:

bufferstd_logic_vector（3downto0）;

ql:

bufferstd_logic）;

endcounter_60;

architecturebhvofcounter_60is

--co<

whenqh="

andql="

anden='

else'

process（clk_1hz,rest,en）

ifrest='

thenqh<

ql<

elsifrising_edge（clk_1hz）then

--ifset='

--qh<

=d（7downto4）;

--ql<

=d（3downto0）;