层次化4位加法器设计 VHDL文档格式.docx
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四．实验原理
通过动态扫描两组4BIT的二进制数据，同时还有一个单BIT的进位，把三者按照二进制加法原理进行加，求出和及进位，并通过电路显示出各部分数据（输入，输出）。
加数、被加数、“和”显示在共阳数码管上，进位输出显示在LED上。
五．程序代码
1、半加器Hadder代码
LIBRARYIeee;
USEIeee.Std_Logic_1164.all;
ENTITYHADDERIS
Port（a,b:
InBit;
Co,So:
OutBit）;
ENDHADDER;
ARCHITECTUREfh1OfHADDERIs
BEGIN
So<
=（aXorb）;
Co<
=（aAndb）;
ENDfh1;
2、或门ora代码
ENTITYoraIS
Port（a:
inStd_Logic;
b:
c:
outStd_Logic）;
ENDora;
ARCHITECTUREorgOForaIS
BEGIN
c<
=aOrb;
ENDorg;
3、1位全加器f_hadder代码
ENTITYf_ADDERIS
Port（x:
InStd_Logic;
y:
cin:
cout:
OutStd_Logic;
sum:
OutStd_Logic）;
ENDf_ADDER;
ARCHITECTUREfd1Off_ADDERIs
ComponentHADDER
Port（a,b:
co,so:
ENDComponent;
Componentora
Port（a,b:
Signald,e,f:
Std_Logic;
Begin
U1:
HADDER
PortMap（a=>
X,b=>
Y,Co=>
d,so=>
e）;
U2:
HADDER
e,b=>
cin,Co=>
f,so=>
sum）;
U3:
oraPortMap（a=>
d,b=>
f,c=>
cout）;
ENDARCHITECTUREfd1;
4、4位全加器Qadd：
Libraryieee;
Useieee.std_logic_1164.all;
EntityQaddis
Port（a:
instd_logic_VECTOR（3DOWNTO0）;
--cin:
instd_logic;
s:
outstd_logic_VECTOR（3DOWNTO0））;
EndQadd;
ArchitectureoneofQaddis
Signalc0,c1,c2,c3:
std_logic;
Componentf_ADDER
ENDComponent;
u1:
F_ADDER
Portmap（sum=>
s（0）,cout=>
c0,X=>
a（0）,Y=>
b（0）,cin=>
'
0'
）;
u2:
F_ADDER
s
（1）,cout=>
c1,X=>
a
（1）,Y=>
b
（1）,cin=>
c0）;
u3:
F_ADDER
s
（2）,cout=>
c2,X=>
a
（2）,Y=>
b
（2）,cin=>
c1）;
u4:
s（3）,cout=>
c3,X=>
a（3）,Y=>
b（3）,cin=>
c2）;
END;
六．仿真结果
程序代码进行编译后，建立waveform文件，设定输入输出端口进行仿真，仿真结果如图1-1所示。
图1-1实验1仿真结果
七．引脚定义及代码：
仿真成功后，在实验箱上进行验证，对其引脚设置的结果的代码为：
Qadd.tcl：
#Copyright（C）1991-2008AlteraCorporation
#YouruseofAlteraCorporation'
sdesigntools,logicfunctions
#andothersoftwareandtools,anditsAMPPpartnerlogic
#functions,andanyoutputfilesfromanyoftheforegoing
#（includingdeviceprogrammingorsimulationfiles）,andany
#associateddocumentationorinformationareexpresslysubject
#tothetermsandconditionsoftheAlteraProgramLicense
#SubscriptionAgreement,AlteraMegaCoreFunctionLicense
#Agreement,orotherapplicablelicenseagreement,including,
#withoutlimitation,thatyouruseisforthesolepurposeof
#programminglogicdevicesmanufacturedbyAlteraandsoldby
#Alteraoritsauthorizeddistributors.Pleaserefertothe
#applicableagreementforfurtherdetails.
#QuartusII:
GenerateTclFileforProject
#File:
qadd.tcl
#Generatedon:
MonOct2614:
44:
092009
#LoadQuartusIITclProjectpackage
packagerequire:
:
quartus:
project
setneed_to_close_project0
setmake_assignments1
#Checkthattherightprojectisopen
if{[is_project_open]}{
if{[stringcompare$quartus（project）"
qadd"
]}{
puts"
Projectqaddisnotopen"
setmake_assignments0
}
}else{
#Onlyopenifnotalreadyopen
if{[project_existsqadd]}{
project_open-revisionqaddqadd
}else{
project_new-revisionqaddqadd
setneed_to_close_project1
}
#Makeassignments
if{$make_assignments}{
set_global_assignment-nameFAMILY"
CycloneII"
set_global_assignment-nameDEVICEEP2C35F672C8
set_global_assignment-nameORIGINAL_QUARTUS_VERSION8.0
set_global_assignment-namePROJECT_CREATION_TIME_DATE"
11:
01:
34OCTOBER26,2009"
set_global_assignment-nameLAST_QUARTUS_VERSION8.0
set_global_assignment-nameUSE_GENERATED_PHYSICAL_CONSTRAINTSOFF-section_ideda_palace
set_global_assignment-nameDEVICE_FILTER_PACKAGEFBGA
set_global_assignment-nameDEVICE_FILTER_PIN_COUNT672
set_global_assignment-nameDEVICE_FILTER_SPEED_GRADE8
set_global_assignment-nameVHDL_FILEora.vhd
set_global_assignment-nameVHDL_FILEHADDER.vhd
set_global_assignment-nameVHDL_FILEf_ADDER.vhd
set_global_assignment-nameVHDL_FILEqadd.vhd
set_global_assignment-namePARTITION_NETLIST_TYPESOURCE-section_idTop
set_global_assignment-namePARTITION_COLOR14622752-section_idTop
set_global_assignment-nameLL_ROOT_REGIONON-section_id"
RootRegion"
set_global_assignment-nameLL_MEMBER_STATELOCKED-section_id"
set_global_assignment-nameVECTOR_WAVEFORM_FILEqadd.vwf
set_global_assignment-nameSIMULATION_MODEFUNCTIONAL
set_global_assignment-nameSTRATIX_DEVICE_IO_STANDARD"
3.3-VLVTTL"
set_global_assignment-nameRESERVE_ALL_UNUSED_PINS"
ASINPUTTRI-STATED"
set_global_assignment-nameINCREMENTAL_VECTOR_INPUT_SOURCEqadd.vwf
set_global_assignment-nameUSE_CONFIGURATION_DEVICEON
set_global_assignment-nameRESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND"
set_instance_assignment-namePARTITION_HIERARCHYroot_partition-to|-section_idTop
set_location_assignmentPIN_B21-tob[0]
set_location_assignmentPIN_B22-tob[1]
set_location_assignmentPIN_AC10-tos[0]
set_location_assignmentPIN_W11-tos[1]
set_location_assignmentPIN_W12-tos[2]
set_location_assignmentPIN_AE8-tos[3]
set_location_assignmentPIN_AF8-tos[4]
set_location_assignmentPIN_AE7-tos[5]
set_location_assignmentPIN_AF7-tos[6]
set_location_assignmentPIN_AA11-tos[7]
set_location_assignmentPIN_F6-toa[0]
set_location_assignmentPIN_A21-toa[1]
#Commitassignments
export_assignments
#Closeproject
if{$need_to_close_project}{
project_close
其引脚图如图1-2所示
图1-2实验1引脚图
八．运行结果
经过JTAG下载后，在实验箱上得到的运行结果如图1-3所示
图1-3实验1运行结果
九．心得体会
升级会员 