2440initsWord文档格式.docx
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]
MACRO
MOV_PC_LR
[THUMBCODE
bxlr
movpc,lr
]
MEND
MOVEQ_PC_LR
bxeqlr
moveqpc,lr
$HandlerLabelHANDLER$HandleLabel
$HandlerLabel
subsp,sp,#4;
decrementsp（tostorejumpaddress）
stmfdsp!
{r0};
PUSHtheworkregistertostack（lrdoesnotpushbecauseitreturntooriginaladdress）
ldrr0,=$HandleLabel;
loadtheaddressofHandleXXXtor0
ldrr0,[r0];
loadthecontents（serviceroutinestartaddress）ofHandleXXX
strr0,[sp,#4];
storethecontents（ISR）ofHandleXXXtostack
ldmfdsp!
{r0,pc};
POPtheworkregisterandpc（jumptoISR）
IMPORT|Image$$RO$$Base|;
BaseofROMcode
IMPORT|Image$$RO$$Limit|;
EndofROMcode（=startofROMdata）
IMPORT|Image$$RW$$Base|;
BaseofRAMtoinitialise
IMPORT|Image$$ZI$$Base|;
Baseandlimitofarea
IMPORT|Image$$ZI$$Limit|;
tozeroinitialise
IMPORTMMU_SetAsyncBusMode
IMPORTMMU_SetFastBusMode;
IMPORTMain;
Themainentryofmonprogram
IMPORTRdNF2SDRAM;
CopyImagefromNandFlashtoSDRAM
AREAInit,CODE,READONLY
ENTRY
EXPORT__ENTRY
__ENTRY
ResetEntry
;
1）Thecode,whichconvertstoBig-endian,shouldbeinlittleendiancode.
2）ThefollowinglittleendiancodewillbecompiledinBig-Endianmode.
Thecodebyteordershouldbechangedasthememorybuswidth.
3）Thepseudoinstruction,DCDcannotbeusedherebecausethelinkergenerateserror.
ASSERT:
DEF:
ENDIAN_CHANGE
[ENDIAN_CHANGE
ASSERT:
ENTRY_BUS_WIDTH
[ENTRY_BUS_WIDTH=32
bChangeBigEndian;
DCD0xea000007
]
[ENTRY_BUS_WIDTH=16
andeqr14,r7,r0,lsl#20;
DCD0x0007ea00
[ENTRY_BUS_WIDTH=8
streqr0,[r0,-r10,ror#1];
DCD0x070000ea
|
bResetHandler
bHandlerUndef;
handlerforUndefinedmode
bHandlerSWI;
handlerforSWIinterrupt
bHandlerPabort;
handlerforPAbort
bHandlerDabort;
handlerforDAbort
b.;
reserved
bHandlerIRQ;
handlerforIRQinterrupt
bHandlerFIQ;
handlerforFIQinterrupt
@0x20
bEnterPWDN;
Mustbe@0x20.
ChangeBigEndian
@0x24
[ENTRY_BUS_WIDTH=32
DCD0xee110f10;
0xee110f10=>
mrcp15,0,r0,c1,c0,0
DCD0xe3800080;
0xe3800080=>
orrr0,r0,#0x80;
//Big-endian
DCD0xee010f10;
0xee010f10=>
mcrp15,0,r0,c1,c0,0
[ENTRY_BUS_WIDTH=16
DCD0x0f10ee11
DCD0x0080e380
DCD0x0f10ee01
[ENTRY_BUS_WIDTH=8
DCD0x100f11ee
DCD0x800080e3
DCD0x100f01ee
DCD0xffffffff;
swinv0xffffffissimilarwithNOPandrunwellinbothendianmode.
DCD0xffffffff
bResetHandler
HandlerFIQHANDLERHandleFIQ
HandlerIRQHANDLERHandleIRQ
HandlerUndefHANDLERHandleUndef
HandlerSWIHANDLERHandleSWI
HandlerDabortHANDLERHandleDabort
HandlerPabortHANDLERHandlePabort
IsrIRQ
reservedforPC
{r8-r9}
ldrr9,=INTOFFSET
ldrr9,[r9]
ldrr8,=HandleEINT0
addr8,r8,r9,lsl#2
ldrr8,[r8]
strr8,[sp,#8]
{r8-r9,pc}
LTORG
=======
ResetHandler
ldrr0,=WTCON;
watchdogdisable
ldrr1,=0x0
strr1,[r0]
ldrr0,=INTMSK
ldrr1,=0xffffffff;
allinterruptdisable
ldrr0,=INTSUBMSK
ldrr1,=0x7fff;
allsubinterruptdisable
[{FALSE}
;
rGPFDAT=（rGPFDAT&
~（0xf<
4））|（（~data&
0xf）<
4）;
Led_Display
ldrr0,=GPBCON
ldrr1,=0x155500
strr1,[r0]
ldrr0,=GPBDAT
ldrr1,=0x0
ToreducePLLlocktime,adjusttheLOCKTIMEregister.
ldrr0,=LOCKTIME
ldrr1,=0xffffff
[PLL_ON_START
Addedforconfirmclockdivide.for2440.
SettingvalueFclk:
Hclk:
Pclk
ldrr0,=CLKDIVN
ldrr1,=CLKDIV_VAL;
0=1:
1:
1,1=1:
2,2=1:
2:
2,3=1:
4,4=1:
4:
4,5=1:
8,6=1:
3:
3,7=1:
6.
programhasnotbeencopied,sousethesedirectly
[CLKDIV_VAL>
1;
meansFclk:
Hclkisnot1:
1.
mrcp15,0,r0,c1,c0,0
orrr0,r0,#0xc0000000;
R1_nF:
OR:
R1_iA
mcrp15,0,r0,c1,c0,0
bicr0,r0,#0xc0000000;
R1_iA:
R1_nF
ConfigureUPLL
ldrr0,=UPLLCON
ldrr1,=（（U_MDIV<
12）+（U_PDIV<
4）+U_SDIV）;
Fin=12.0MHz,UCLK=48MHz
nop;
Caution:
AfterUPLLsetting,atleast7-clocksdelaymustbeinsertedforsettinghardwarebecompleted.
nop
ConfigureMPLL
ldrr0,=MPLLCON
ldrr1,=（（M_MDIV<
12）+（M_PDIV<
4）+M_SDIV）;
Fin=12.0MHz,FCLK=400MHz
Checkifthebootiscausedbythewake-upfromSLEEPmode.
ldrr1,=GSTATUS2
ldrr0,[r1]
tstr0,#0x2
Incaseofthewake-upfromSLEEPmode,gotoSLEEP_WAKEUPhandler.
bneWAKEUP_SLEEP
EXPORTStartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp
Setmemorycontrolregisters
ldrr0,=SMRDATA
adrlr0,SMRDATA;
becareful!
ldrr1,=BWSCON;
BWSCONAddress
addr2,r0,#52;
EndaddressofSMRDATA
ldrr3,[r0],#4
strr3,[r1],#4
cmpr2,r0
bne%B0
WhenEINT0ispressed,ClearSDRAM
checkifEIN0buttonispressed
ldrr0,=GPFCON
ldrr0,=GPFUP
ldrr1,=0xff
ldrr1,=GPFDAT
bicr0,r0,#（0x1e<
1）;
bitclear
tstr0,#0x1
bne%F1
ClearSDRAMStart
ldrr1,=0x55aa
ldrr0,=GPFDAT
strr1,[r0];
LED=****
movr1,#0
movr2,#0
movr3,#0
movr4,#0
movr5,#0
movr6,#0
movr7,#0
movr8,#0
ldrr9,=0x4000000;
64MB
ldrr0,=0x30000000
0
stmiar0!
{r1-r8}
subsr9,r9,#32
ClearSDRAMEnd
1
Initializestacks
blInitStacks
===========================================================
ldrr0,=BWSCON
ldrr0,[r0]
andsr0,r0,#6;
OM[1:
0]!
=0,NORFLashboot
bnecopy_proc_beg;
donotreadnandflash
adrr0,ResetEntry;
0]==0,NANDFLashboot
cmpr0,#0;
ifuseMulti-ice,
donotreadnandflashforboot
nop
nand_boot_beg
[{TRUE}
blRdNF2SDRAM
ldrpc,=copy_proc_beg
copy_proc_beg
adrr0,ResetEntry
ldrr2,BaseOfROM
cmpr0,r2
ldreqr0,TopOfROM
beqInitRam
ldrr3,TopOfROM
ldmiar0!
{r4-r7}
stmiar2!
cmpr2,r3
bcc%B0
subr2,r2,r3
subr0,r0,r2
InitRam
ldrr2,BaseOfBSS
ldrr3,BaseOfZero
ldrccr1,[r0],#4
strccr1,[r2],#4
bcc%B0
movr0,#0
ldrr3,EndOfBSS
1
strccr0,[r2],#4
bcc%B1
ldrpc,=%F2;
gotocompileraddress
2
[CLKDIV_VAL>
blMMU_SetAsyncBusMode
|
blMMU_SetFastBusMode;
defaultvalue.
SetupIRQhandler
ldrr0,=HandleIRQ;
Thisroutineisneeded
ldrr1,=IsrIRQ;
ifthereisnot'
subspc,lr,#4'
at0x18,0x1c
[:
LNOT:
THUMBCODE
blMain;
Donotusemain（）because......
b.
[THUMBCODE;
forstart-upcodeforThumbmode
orrlr,pc,#1
bxlr
CODE16
CODE32
functioninitializingstacks
InitStacks
DonotuseDRAM,suchasstmfd,ldmfd......
SVCstackisinitializedbefore
Undertoolkitver2.5,'
msrcpsr,r1'
canbeusedinsteadof'
msrcpsr_cxsf,r1'
mrsr0,cpsr
bicr0,r0,#MODEMASK
orrr1,r0,#UNDEFMODE|NOINT
msrcpsr_cxsf,r1;
UndefMode
ldrsp,=UndefStack;
UndefStack=0x33FF_5C00
orrr1,r0,#ABORTMODE|NOINT
AbortMode
ldrsp,=AbortStack;
AbortStack=0x33FF_6000
orrr1,r0,#IRQMODE|NOINT
IRQMode
ldrsp,=IRQStack;
IRQStack=0x33FF_7000
orrr1,r0,#FIQMODE|NOINT
FIQMode
ldrsp,=FIQStack;
FIQStack=0x33FF_8000
bicr0,r0,#MODEMASK|NOINT
orrr1,r0,#SVCMODE
SVCMode
ldrsp,=SVCStack;
SVCStack=0x33FF_5800
USERmodehasnotbeinitialized.
TheLRregisterwillnotbevalidifthecurrentmodeisnotSVCmode.
SMRDATADATA
Memoryconfigurationshouldbeoptimizedforbestperformance
Thefollowingparameterisnotoptimized.
Memoryaccesscycleparameterstrategy
1）ThememorysettingsissafeparametersevenatHCLK=75Mhz.
2）SDRAMrefreshperiodisforHCLK<
=75Mhz.
DCD（0+（B1_BWSCON<
4）+（B2_BWSCON<
8）+（B3_BWSCON<
12）+（B4_BWSCON<
16）+（B5_BWSCON<
20）+（B6_BWSCON<
24）+（B7_BWSCON<
28））
DCD（（B0_Tacs<
13）+（B0_Tcos<
11）+（B0_Tacc<
8）+（B0_Tcoh<
6）+（B0_Tah<
4）+（B0_Tacp<
2）+（B0_PMC））;
GCS0
DCD（（B1_Tacs<
13）+（B1_Tcos<
11）+（B1_Tacc<
8）+（B1_Tcoh<
6）+（B1_Tah<
4）+（B1_
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