2440initsWord文档格式.docx

1、 MACRO MOV_PC_LR THUMBCODE bx lr mov pc,lr MEND MOVEQ_PC_LR bxeq lr moveq pc,lr$HandlerLabel HANDLER $HandleLabel$HandlerLabel sub sp,sp,#4 ;decrement sp（to store jump address） stmfd sp!,r0 ;PUSH the work register to stack（lr does not push because it return to original address） ldr r0,=$HandleLabel;

2、load the address of HandleXXX to r0 ldr r0,r0 ;load the contents（service routine start address） of HandleXXX str r0,sp,#4 ;store the contents（ISR） of HandleXXX to stack ldmfd sp!,r0,pc ;POP the work register and pc（jump to ISR） IMPORT |Image$RO$Base| ; Base of ROM code IMPORT |Image$RO$Limit| ; End

3、of ROM code （=start of ROM data） IMPORT |Image$RW$Base| ; Base of RAM to initialise IMPORT |Image$ZI$Base| ; Base and limit of area IMPORT |Image$ZI$Limit| ; to zero initialise IMPORT MMU_SetAsyncBusMode IMPORT MMU_SetFastBusMode ; IMPORT Main ; The main entry of mon program IMPORT RdNF2SDRAM ; Copy

4、 Image from Nand Flash to SDRAM AREA Init,CODE,READONLY ENTRY EXPORT _ENTRY_ENTRYResetEntry ;1）The code, which converts to Big-endian, should be in little endian code.2）The following little endian code will be compiled in Big-Endian mode. The code byte order should be changed as the memory bus width

5、.3）The pseudo instruction,DCD can not be used here because the linker generates error. ASSERT :DEF:ENDIAN_CHANGE ENDIAN_CHANGE ASSERT :ENTRY_BUS_WIDTH ENTRY_BUS_WIDTH=32 b ChangeBigEndian ;DCD 0xea000007 ENTRY_BUS_WIDTH=16 andeq r14,r7,r0,lsl #20 ;DCD 0x0007ea00 ENTRY_BUS_WIDTH=8 streq r0,r0,-r10,ro

6、r #1 ;DCD 0x070000ea | b ResetHandler b HandlerUndef ;handler for Undefined mode b HandlerSWI ;handler for SWI interrupt b HandlerPabort ;handler for PAbort b HandlerDabort ;handler for DAbort b . ;reserved b HandlerIRQ ;handler for IRQ interrupt b HandlerFIQ ;handler for FIQ interrupt0x20 b EnterPW

7、DN ; Must be 0x20.ChangeBigEndian0x24 ENTRY_BUS_WIDTH=32 DCD 0xee110f10 ;0xee110f10 = mrc p15,0,r0,c1,c0,0 DCD 0xe3800080 ;0xe3800080 = orr r0,r0,#0x80; /Big-endian DCD 0xee010f10 ;0xee010f10 = mcr p15,0,r0,c1,c0,0 ENTRY_BUS_WIDTH=16 DCD 0x0f10ee11 DCD 0x0080e380 DCD 0x0f10ee01 ENTRY_BUS_WIDTH=8 DCD

8、 0x100f11ee DCD 0x800080e3 DCD 0x100f01ee DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode. DCD 0xffffffff b ResetHandlerHandlerFIQ HANDLER HandleFIQHandlerIRQ HANDLER HandleIRQHandlerUndef HANDLER HandleUndefHandlerSWI HANDLER HandleSWIHandlerDabort HANDLER Handle

9、DabortHandlerPabort HANDLER HandlePabortIsrIRQreserved for PC,r8-r9 ldr r9,=INTOFFSET ldr r9,r9 ldr r8,=HandleEINT0 add r8,r8,r9,lsl #2 ldr r8,r8 str r8,sp,#8,r8-r9,pc LTORG=ResetHandler ldr r0,=WTCON ;watch dog disable ldr r1,=0x0 str r1,r0 ldr r0,=INTMSK ldr r1,=0xffffffff ;all interrupt disable l

10、dr r0,=INTSUBMSK ldr r1,=0x7fff ;all sub interrupt disable FALSE ;rGPFDAT = （rGPFDAT & （0xf4） | （data & 0xf）1 ; means Fclk:Hclk is not 1:1. mrc p15,0,r0,c1,c0,0 orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA mcr p15,0,r0,c1,c0,0 bic r0,r0,#0xc0000000;R1_iA:R1_nFConfigure UPLL ldr r0,=UPLLCON ldr r1,=（U_MDIV12

11、）+（U_PDIV4）+U_SDIV） ;Fin = 12.0MHz, UCLK = 48MHz nop ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed. nopConfigure MPLL ldr r0,=MPLLCON ldr r1,=（M_MDIV12）+（M_PDIV4）+M_SDIV） ;Fin = 12.0MHz, FCLK = 400MHzCheck if the boot is caused by the wake-

12、up from SLEEP mode. ldr r1,=GSTATUS2 ldr r0,r1 tst r0,#0x2In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler. bne WAKEUP_SLEEP EXPORT StartPointAfterSleepWakeUpStartPointAfterSleepWakeUpSet memory control registersldr r0,=SMRDATA adrl r0, SMRDATA ;be careful! ldr r1,=BWSCON ;BWSCON A

13、ddress add r2, r0, #52 ;End address of SMRDATA ldr r3, r0, #4 str r3, r1, #4 cmp r2, r0 bne %B0 When EINT0 is pressed, Clear SDRAM check if EIN0 button is pressed ldr r0,=GPFCON ldr r0,=GPFUP ldr r1,=0xff ldr r1,=GPFDAT bic r0,r0,#（0x1e bl MMU_SetAsyncBusMode | bl MMU_SetFastBusMode ; default value.

14、 Setup IRQ handler ldr r0,=HandleIRQ ;This routine is needed ldr r1,=IsrIRQ ;if there is not subs pc,lr,#4 at 0x18, 0x1c :LNOT:THUMBCODE bl Main ;Do not use main（） because . b . THUMBCODE ;for start-up code for Thumb mode orr lr,pc,#1 bx lr CODE16 CODE32function initializing stacksInitStacksDo not u

15、se DRAM,such as stmfd,ldmfd.SVCstack is initialized beforeUnder toolkit ver 2.5, msr cpsr,r1 can be used instead of msr cpsr_cxsf,r1 mrs r0,cpsr bic r0,r0,#MODEMASK orr r1,r0,#UNDEFMODE|NOINT msr cpsr_cxsf,r1 ;UndefMode ldr sp,=UndefStack ; UndefStack=0x33FF_5C00 orr r1,r0,#ABORTMODE|NOINTAbortMode

16、ldr sp,=AbortStack ; AbortStack=0x33FF_6000 orr r1,r0,#IRQMODE|NOINTIRQMode ldr sp,=IRQStack ; IRQStack=0x33FF_7000 orr r1,r0,#FIQMODE|NOINTFIQMode ldr sp,=FIQStack ; FIQStack=0x33FF_8000 bic r0,r0,#MODEMASK|NOINT orr r1,r0,#SVCMODESVCMode ldr sp,=SVCStack ; SVCStack=0x33FF_5800USER mode has not be

17、initialized.The LR register will not be valid if the current mode is not SVC mode.SMRDATA DATA Memory configuration should be optimized for best performance The following parameter is not optimized. Memory access cycle parameter strategy 1） The memory settings is safe parameters even at HCLK=75Mhz. 2） SDRAM refresh period is for HCLK=75Mhz. DCD （0+（B1_BWSCON4）+（B2_BWSCON8）+（B3_BWSCON12）+（B4_BWSCON16）+（B5_BWSCON20）+（B6_BWSCON24）+（B7_BWSCON28） DCD （B0_Tacs13）+（B0_Tcos11）+（B0_Tacc8）+（B0_Tcoh6）+（B0_Tah4）+（B0_Tacp2）+（B0_PMC） ;GCS0 DCD （B1_Tacs13）+（B1_Tcos11）+（B1_Tacc8）+（B1_Tcoh6）+（B1_Tah4）+（B1_