利用按键开关控制点阵进行八进制数字显示Word文档下载推荐.docx
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1.分频模块(FENPIN):
对时钟进行1000分频。
图2分频模块图及管脚
libraryieee;
Useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpinis
port(clk:
instd_logic;
clkout:
outstd_logic);
endfenpin;
architecturer1offenpinis
signalcnt:
integerrange0to15;
begin
process(clk)
begin
ifclk'
eventandclk='
1'
then
ifcnt<
8then
clkout<
='
0'
;
else
endif;
cnt<
=cnt+1;
endprocess;
endr1;
2.消斗模块(XIAODOU):
对按键信号进行消斗,使案件输出稳定,最终使点阵显示稳定。
图3消抖模块图及管脚
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityxiaodouis
port(
clk:
instd_logic;
rst:
d_click:
outstd_logic;
click:
instd_logic
);
endxiaodou;
architecturer1ofxiaodouis
signalcount:
integerrange0to10000;
--std_logic_vector(9downto0);
signalcount1:
std_logic_vector(7downto0);
signaldout1:
std_logic;
begin
process(clk,rst)
ifrst='
dout1<
count1<
="
00000000"
elsifclk'
eventandclk='
if(click='
)and(count1(7)='
)and(dout1='
)then
=count1+1;
elsif(click='
d_click<
=dout1;
endprocess;
3.计数模块(JISHU):
进行八进制计数,输出控制显示模块的CH[2..0]。
图4计数模块及管脚图
entityjishuis
port(clk:
count:
outstd_logic_vector(2downto0));
endjishu;
architecturer1ofjishuis
signalcn:
std_logic_vector(2downto0);
count<
=cn;
process(clk,rst)
ifrst='
cn<
000"
elsifclk'
ifcn="
111"
=cn+1;
endif;
4.功能控制模块(CNTA):
利用时钟进行十六进制计数,控制列信号从0000-1111变化。
图5功能控制模块及管脚图
useieee.std_logic_1164.all;
entitycntais
port(clk:
q:
outstd_logic_vector(3downto0));
endcnta;
architecturer1ofcntais
process(clk)
variabletmp:
std_logic_vector(3downto0);
ifclk'
iftmp="
1111"
tmp:
="
0000"
=tmp+1;
q<
=tmp-1;
5.16×
16点阵显示(XIANSHI):
用CH[2..0]与SEL[3..0]控制显示从0-7八个数字。
图6显示模块及其管脚图
entityxianshiis
port(ch:
instd_logic_vector(2downto0);
sel:
instd_logic_vector(3downto0);
dout:
outstd_logic_vector(15downto0));
endxianshi;
architecturer1ofxianshiis
process(ch,sel)
casechis
when"
=>
caseselis
=>
dout<
0000000000000000"
when"
0001"
0000011111100000"
0010"
0000111111110000"
0011"
0001111111111000"
0100"
0011000000001100"
0101"
0110"
0111"
1000"
1001"
1010"
1011"
1100"
1101"
1110"
whenothers=>
null;
endcase;
001"
0000000000000100"
0001111111111100"
0000100000000100"
when"
010"
caseselis
0000000000010000"
0000111000011100"
0001111100001100"
when"
0001111110001100"
0001000110001100"
0001000011001100"
0001000001001100"
0001000001101100"
0001000000101100"
0001000000111100"
0001111000011100"
0000111000001100"
0000010000001100"
whenothers=>
null;
011"
0000000000100000"
0000010001111000"
0000111001111000"
0001111111011100"
0001101110000100"
0001000110000100"
0001000000000100"
0001110000011100"
0000110000011100"
0000110000011000"
100"
0000000000100100"
0000110000100100"
0000011000100100"
0000001000100100"
0000000100100000"
0000000110100000"
0000000011100000"
0000000001100000"
endcase;
101"
0001000011110000"
0001000111111000"
0001001111011100"
0001001100000100"
0001111110011100"
0001111110111000"
0000000000011000"
110"
0000000001110000"
0000100011111000"
0001110111111000"
0001100110001100"
0001100100000100"
0001000100000100"
0000111111111000"
0000011111111000"
0000001111110000"
0000000011000000"
0001000000000000"
0001100000000000"
0001110000000000"
0001011000000000"
0001001100000000"
0001000111000000"
0001000011111100"
0001000001111100"
0000110000000000"
whenothe