1、1分频模块(FENPIN):对时钟进行1000分频。图2 分频模块图及管脚library ieee;Use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin is port(clk:in std_logic; clkout:out std_logic);end fenpin;architecture r1 of fenpin issignal cnt:integer range 0 to 15;begin process(clk) begin if clkevent and clk=1 then if c
2、nt8 then clkout = 0; else end if; cnt = cnt +1; end process;end r1;2.消斗模块(XIAODOU):对按键信号进行消斗,使案件输出稳定,最终使点阵显示稳定。图3 消抖模块图及管脚library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity xiaodou is port( clk : in std_logic; rst : d_click : out std_logic; c
3、lick : in std_logic );end xiaodou;architecture r1 of xiaodou is signal count : integer range 0 to 10000;-std_logic_vector(9 downto 0); signal count1 : std_logic_vector(7 downto 0); signal dout1 : std_logic;beginprocess (clk,rst) if rst = dout1 count1 = 00000000 elsif clk event and clk = if (click =
4、) and (count1(7) = ) and (dout1 = ) then= count1+1; elsif (click = d_click = dout1; end process;3.计数模块(JISHU):进行八进制计数,输出控制显示模块的CH2.0 。图4 计数模块及管脚图entity jishu isport( clk : count : out std_logic_vector(2 downto 0);end jishu;architecture r1 of jishu issignal cn : std_logic_vector(2 downto 0); count =
5、cn;process(clk,rst)if rst = cn 000elsif clk if cn = 111= cn+1;end if;4.功能控制模块(CNTA):利用时钟进行十六进制计数,控制列信号从0000-1111变化。图5 功能控制模块及管脚图use ieee.std_logic_1164.all;entity cnta isport(clk: q:out std_logic_vector(3 downto 0);end cnta;architecture r1 of cnta isprocess(clk) variable tmp:std_logic_vector(3 downt
6、o 0);if clk if tmp=1111 tmp:=0000=tmp+1;q case sel is = doutnull; end case;001000000000000010000011111111111000000100000000100when 010 case sel is000000000001000000001110000111000001111100001100 when 0001111110001100000100011000110000010000110011000001000001001100000100000110110000010000001011000001
7、000000111100000111100001110000001110000011000000010000001100 when others = null;0110000000000100000000001000111100000001110011110000001111111011100000110111000010000010001100001000001000000000100000111000001110000001100000111000000110000011000100000000000010010000001100001001000000011000100100000000
8、10001001000000000100100000000000011010000000000000111000000000000001100000 end case;10100010000111100000001000111111000000100111101110000010011000001000001111110011100000111111011100000000000000110001100000000001110000000010001111100000011101111110000001100110001100000110010000010000010001000001000000111111111000000001111111100000000011111100000000000011000000000100000000000000011000000000000001110000000000000101100000000000010011000000000001000111000000000100001111110000010000011111000000110000000000 when othe
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