完整word版数字密码器的设计VHDL语言.docx

完整word版数字密码器的设计VHDL语言.docx

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完整word版数字密码器的设计VHDL语言

石家庄铁道大学数字电路课程设计

数字电路课程设计

--VHDL语言设计

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石家庄铁道大学数字电路课程设计

基于VHDL的数字密码器的设计

【摘要】本论文介绍了一种利用EDA技术和VHDL语言，通过自顶向下的设计方法对数字密码器进行设计，并在FPGA芯片EPF10K10LC84-4上实现。

用FPGA器件构造系统,所有算法完全由硬件电路来实现,使得系统的工作可靠性大为提高。

由于FPGA具有ISP（在系统可编程）功能,当设计需要更改时,只需更改FPGA中的控制和接口电路,利用EDA工具将更新后的设计下载到FPGA

中即可,无需更改外部电路的设计,大大提高了设计的效率。

因此,采用FPGA开发的数字系统,不仅具有很高的工作可靠性,其升级与改进也极其方便。

本文设计的密码器采用6位密码,比一般的四位密码锁具有更高的安全可靠性,应用前景十分良好。

【关键词】数字密码器EDAVHDL自顶向下FPGA

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石家庄铁道大学数字电路课程设计

摘要2·································································································································1EDA技术概述5················································································································1.1现代电子设计方法—EDA技术5····················································································1.1.1EDA技术的发展历程5··························································································1.1.2EDA技术的基本特征5··························································································1.1.3EDA技术的发展趋势6·····························································································1.2硬件描述语言（VHDL）简介5··························································································

1.2.1VHDL的产生与发展7·······························································································1.2.2VHDL的基本特征7··································································································1.2.3VHDL的设计流程··································································································6

1.3可编程逻辑器件（PLD）简介7························································································

1.3.1PLD的发展历程7···································································································1.3.2FPGA/CPLD简介8···································································································1.3.3用FPGA/CPLD进行开发的优点8·················································································2数字密码器的VHDL设计10······························································································2.1数字密码器的总体方案设计10·························································································

2.1.1数字密码器的功能描述10························································································2.1.2数字密码器的内部结构及模块划分11·········································································2.1.3数字密码器的工作过程12························································································2.2数字密码器的顶层设计13···························································································2.2.1顶层模块的输入输出13···························································································2.2.1模块描述13············································································································2.2.2VHDL设计14··········································································································2.3数字密码器的底层设计14·······························································································

2.3.1分频模块14···········································································································2.3.2消抖同步模块15·····································································································2.3.3使能电路模块16·····································································································2.3.4密码预置输出模块17·······························································································2.3.5编码模块17···········································································································2.3.6比较模块18···········································································································2.3.7计数器选择模块18··································································································2.3.8数码管显示译码模块19···························································································3

石家庄铁道大学数字电路课程设计

2.3.9数码管扫描模块19··································································································2.3.10指示电路模块20···································································································2.3.11误码模块21··········································································································2.3.12控制器模块21······································································································3数字密码器的VHDL程序的编译、综合、仿真、验证24···················································3.1编译、综合24·····················································································