EDA交通灯控制器课程设计报告书.docx
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EDA交通灯控制器课程设计报告书
交通灯控制器课程设计
该交通信号控制器控制十字路甲、乙两条道路的红、黄和绿三色灯，指挥车辆和行人
安全通行。
功能要求如下：
1.只有在小路上发现汽车时，高速公路上的交通灯才可能变成红灯。
2.当汽车行驶在小路上时，小路的交通灯保持为绿灯，但不能超过给定的时间。
（20s）
3.高速公路灯转为绿色后，即使小路上有汽车出现，而高速公路上并无汽车，也将在给定的时间内保持绿灯。
（60s）。
N
N
Y
Y
N
Y
NY
设计如下：
——1hz分频器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityfen_pin1is
port（clk100hz:
instd_logic;
clk1hz:
outstd_logic）;
endfen_pin1;
architecturebhvoffen_pin1is
signalqan:
std_logic_vector（3downto0）;
signalqbn:
std_logic_vector（3downto0）;
signalcin:
std_logic;
begin
process（clk100hz）
begin
if（clk100hz'eventandclk100hz='1'）then
ifqan="1001"thenqan<="0000";cin<='1';
elseqan<=qan+1;cin<='0';
endif;
endif;
endprocess;
process（clk100hz,cin）
begin
if（clk100hz'eventandclk100hz='1'）then
ifcin='1'then
ifqbn="1001"thenqbn<="0000";
elseqbn<=qbn+1;
endif;
endif;
endif;
endprocess;
process（qan,qbn）
begin
if（qan="1001"andqbn="1001"）thenclk1hz<='1';
elseclk1hz<='0';
endif;
endprocess;
endbhv;
——2hz分频器
libraryieee;
useieee.std_logic_1164.all;
entityfen_pin2is
port（clk100hz:
instd_logic;
clk2hz:
outstd_logic）;
endfen_pin2;
architecturebhvoffen_pin2is
begin
process（clk100hz）
variablecnt:
integerrange0to24;
variabletmp:
std_logic;
begin
if（clk100hz'eventandclk100hz='1'）then
ifcnt=24then
cnt:
=0;
tmp:
=nottmp;
else
cnt:
=cnt+1;
endif;
endif;
clk2hz<=tmp;
endprocess;
endbhv;
——主干道控制
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycontralzis
port（clk:
instd_logic;
ra,ga,ya:
outstd_logic;
timeah,timeal:
outstd_logic_vector（3downto0））;
endcontralz;
architecturebhvofcontralzis
typergis（green,red,yellow2）;
begin
process（clk）
variablea:
std_logic;
variableth,tl:
std_logic_vector（3downto0）;
variablestate:
rg;
begin
ifclk'eventandclk='1'then
casestateis
whengreen=>ifa='0'then
th:
="0101";
tl:
="1001";
a:
='1';
ga<='1';
ra<='0';
ya<='0';
else
ifnot（th="0000"andtl="0001"）then
iftl="0000"then
tl:
="1001";
th:
=th-1;
else
tl:
=tl-1;
endif;
else
th:
="0000";
tl:
="0000";
a:
='0';
state:
=red;
endif;
endif;
whenred=>ifa='0'then
th:
="0001";
tl:
="1001";
a:
='1';
ra<='1';
ya<='0';
ga<='0';
else
ifnot（th="0000"andtl="0001"）then
iftl="0000"then
tl:
="1001";
th:
=th-1;
else
tl:
=tl-1;
endif;
else
th:
="0000";
tl:
="0000";
a:
='0';
ra<='0';
ga<='0';
state:
=yellow2;
endif;
endif;
whenyellow2=>ifa='0'then
th:
="0000";
tl:
="1001";
a:
='1';
ya<='1';
ga<='0';
ra<='0';
else
ifnot（th="0000"andtl="0001"）then
iftl="0000"then
tl:
="1001";
th:
=th-1;
else
tl:
=tl-1;
endif;
else
th:
="0000";
tl:
="0000";
ga<='0';
ra<='0';
ya<='0';
a:
='0';
state:
=green;
endif;
endif;
endcase;
endif;
timeah<=th;
timeal<=tl;
endprocess;
endbhv;
——支路控制
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycontralxis
port（clk:
instd_logic;
rb,gb,yb,chu:
outstd_logic;
timeah,timeal:
outstd_logic_vector（3downto0））;
endcontralx;
architecturebhvofcontralxis
typergyis（red,yellow1,green,yellow2）;
begin
process（clk）
variablea:
std_logic;
variableth,tl:
std_logic_vector（3downto0）;
variablestate:
rgy;
begin
ifclk'eventandclk='1'then
casestateis
whenyellow1=>ifa='0'then
th:
="0000";
tl:
="0100";
a:
='1';
yb<='1';
gb<='0';
rb<='0';
chu<='1';
else
ifnot（th="0000"andtl="0001"）then
iftl="0000"then
tl:
="1001";
th:
=th-1;
else
tl:
=tl-1;
endif;
else
th:
="0000";
tl:
="0000";
a:
='0';
state:
=green;
endif;
endif;
whengreen=>ifa='0'then
th:
="0001";
tl:
="1001";
a:
='1';
gb<='1';
rb<='0';
yb<='0';
chu<='1';
else
ifnot（th="0000"andtl="0001"）then
iftl="0000"then
tl:
="1001";
th:
=th-1;
else
tl:
=tl-1;
endif;
else
th:
="0000";
tl:
="0000";
a:
='0';
state:
=yellow2;
endif;
endif;
whenred=>ifa='0'then
th:
="0101";
tl:
="0100";
a:
='1';
rb<='1';
yb<='0';
chu<='1';
else
ifnot（th="0000"andtl="0001"）then
iftl="0000"then
tl:
="1001";
th:
=th-1;
else
tl:
=tl-1;
endif;
else
th:
="0000";
tl:
="0000";
a:
='0';
state:
=yellow1;
endif;
endif;
whenyellow2=>ifa='0'then
th:
="0000";
tl:
="0100";
a:
='1';
yb<='1';
gb<='0';
rb<='0';
chu<='1';
else
ifnot（th="0000"andtl="0001"）then
iftl="0000"then
tl:
="1001";
th:
=th-1;
else
tl:
=tl-1;
endif;
else
th:
="0000";
tl:
="0000";
a:
='0';
chu<='0';
state:
=red;
endif;
endif;
endcase;
endif;
timeah<=th;
timeal<=tl;
endprocess;
endbhv;
——反馈器
libraryieee;
useieee.std_logic_1164.all;
entitysmenis
port（sm,re,gr,ye:
instd_logic;
jinji:
outstd_logic）;
endsmen;
architectureseofsmenis
begin
processis
begin
if（sm='1'andre='0'andgr='0'andye='0'）thenjinji<='1';
else
jinji<='0';
endif;
endprocess;
endse;
——消抖电路
libraryieee;
useieee.std_logic_1164.all;
entityxiaodouis
port（jinji,clk1hz:
instd_logic;
b:
outstd_logic）;
endxiaodou;
architecturebhvofxiaodouis
signaltemp1:
std_logic;
begin
process（clk1hz,jinji）
variabletemp2:
std_logic;
begin
if（clk1hz'eventandclk1hz='0'）then
temp1<=jinji;
temp2:
=nottemp1;
endif;
b<=temp1andtemp2andclk1hz;
endprocess;
endbhv;
——状态转换
libraryieee;
useieee.std_logic_1164.all;
entitynois
port（a:
instd_logic;
en:
outstd_logic）;
endno;
architectureno_arcofnois
begin
process（a）
variabletmp:
std_logic;
begin
if（a'eventanda='1'）then
tmp:
=nottmp;
endif;
en<=tmp;
endprocess;
endno_arc;
——mux4l
libraryieee;
useieee.std_logic_1164.all;
entitymux41is
port（sel:
instd_logic_vector（2downto0）;
d0,d1,d2,d3:
instd_logic_vector（3downto0）;
q:
outstd_logic_vector（3downto0）;
so:
outstd_logic_vector（1downto0））;
endmux41;
architecturebhvofmux41is
begin
process（sel）
begin
caseselis
when"100"=>q<=d2;so<="00";
when"101"=>q<=d3;so<="01";
when"000"=>q<=d0;so<="10";
whenothers=>q<=d1;so<="11";
endcase;
endprocess;
endbhv;
——译码器
libraryieee;
useieee.std_logic_1164.all;
entitydec7sis
port（d:
instd_logic_vector（3downto0）;
q0,q1,q2,q3,q4,q5,q6:
outstd_logic）;
enddec7s;
architecturebhvofdec7sis
begin
process（d）
variableq:
std_logic_vector（6downto0）;
begin
casedis
when"0000"=>q:
="0111111";
when"0001"=>q:
="0000110";
when"0010"=>q:
="1011011";
when"0011"=>q:
="1001111";
when"0100"=>q:
="1100110";
when"0101"=>q:
="1101101";
when"0110"=>q:
="1111101";
when"0111"=>q:
="0100111";
when"1000"=>q:
="1111111";
when"1001"=>q:
="1101111";
whenothers=>q:
="1111001";
endcase;
q0<=q（0）;
q1<=q
（1）;
q2<=q
（2）;
q3<=q（3）;
q4<=q（4）;
q5<=q（5）;
q6<=q（6）;
endprocess;
endbhv;
仿真图如下：
Ya,ra,ga表示主干道黄红绿灯；yb,rb,gb表示乡村小路黄红绿灯。
下图表示：
主路绿灯60s，红灯20s,黄灯5s，即使中途来车也不发生跳转。
下图说明：
175s之后再无车来，则保持主路绿灯，支路红灯
1~200s仿真图如下;
升级会员 