北邮数电实验VHDL源代码完整综述.docx

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北邮数电实验VHDL源代码完整综述.docx

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北邮数电实验VHDL源代码完整综述.docx

北邮数电实验VHDL源代码完整综述

北邮数电实验VHDL源代码完整版

注：

北邮信通院数电实验，大二下共四次实验，以下为四次实验的完整代码，仅供参考，希望学弟学妹在抄代码的时候了解每一行代码的含义。

知识是自己的。

别忘了，北邮的未来靠你们。

注意事项：

1学校部分电脑打不开07版word文件（后缀docx），建议大家准备一份TXT以防万一

2运行出错时可能是你输入有误，比如中文和英文符号弄错了

3数电实验很简单，但要心细，一定要按老师说的做

4数电实验报告千万不要抄袭，老师判断力很强

实验一：

半加器老师会给出，全加器是画图，怎么画书上有，不用源代码。

实验二：

（1）3位二进制数比较器

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYcomp3IS

PORT（A:

INSTD_LOGIC_VECTOR（2DOWNTO0）;

YA,YB,YC:

OUTSTD_LOGIC）;

ENDcomp3;

ARCHITECTUREbehaveOFcomp3IS

BEGIN

PROCESS（A,B）

BEGIN

IF（A>B）THEN

YA<='1';YB<='0';YC<='0';

ELSIF（A

YA<='0';YB<='1';YC<='0';

ELSE

YA<='0';YB<='0';YC<='1';

ENDIF;

ENDPROCESS;

ENDbehave;

（2）4选1数据选择器

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYmux4IS

PORT（A:

INSTD_LOGIC_VECTOR（1DOWNTO0）;

D0,D1,D2,D3:

INSTD_LOGIC;

Y,YB:

OUTSTD_LOGIC）;

ENDmux4;

ARCHITECTUREbehaveOFmux4IS

BEGIN

PROCESS（A,D0,D1,D2,D3）

BEGIN

CASEAIS

WHEN"00"=>Y<=D0;YB<=NOTD0;

WHEN"01"=>Y<=D1;YB<=NOTD1;

WHEN"10"=>Y<=D2;YB<=NOTD2;

WHEN"11"=>Y<=D3;YB<=NOTD3;

WHENOTHERS=>Y<='Z';YB<='Z';

ENDCASE;

ENDPROCESS;

ENDbehave;

（3）8421码转换为格雷码

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYtrans1IS

PORT（A:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

OUTSTD_LOGIC_VECTOR（3DOWNTO0））;

ENDtrans1;

ARCHITECTUREtrans_grayOFtrans1IS

BEGIN

B（0）<=A（0）XORA

（1）;

（1）<=A

（1）XORA

（2）;

（2）<=A

（2）XORA（3）;

B（3）<=A（3）;

ENDtrans_gray;

（4）8421码转换为余三码

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYsunyu_trans2IS

PORT（A:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

OUTSTD_LOGIC_VECTOR（3DOWNTO0））;

ENDsunyu_trans2;

ARCHITECTUREtrans_ex3OFsunyu_trans2IS

BEGIN

PROCESS（A）

BEGIN

CASEAIS

WHEN"0000"=>B<="0011";

WHEN"0001"=>B<="0100";

WHEN"0010"=>B<="0101";

WHEN"0011"=>B<="0110";

WHEN"0100"=>B<="0111";

WHEN"0101"=>B<="1000";

WHEN"0110"=>B<="1001";

WHEN"0111"=>B<="1010";

WHEN"1000"=>B<="1011";

WHEN"1001"=>B<="1100";

WHENOTHERS=>B<="ZZZZ";

ENDCASE;

ENDPROCESS;

ENDtrans_ex3;

（5）数码管译码器

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYsunyu_encoderIS

PORT（A:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

OUTSTD_LOGIC_VECTOR（6DOWNTO0）;

OUTSTD_LOGIC_VECTOR（5DOWNTO0））;

ENDsunyu_encoder;

ARCHITECTUREencoder_archOFsunyu_encoderIS

BEGIN

PROCESS（A）

BEGIN

C<="011111";

CASEAIS

WHEN"0000"=>B<="1111110";--0

WHEN"0001"=>B<="0110000";--1

WHEN"0010"=>B<="1101101";--2

WHEN"0011"=>B<="1111001";--3

WHEN"0100"=>B<="0110011";--4

WHEN"0101"=>B<="1011011";--5

WHEN"0110"=>B<="1011111";--6

WHEN"0111"=>B<="1110000";--7

WHEN"1000"=>B<="1111111";--8

WHEN"1001"=>B<="1111011";--9

WHENOTHERS=>B<="ZZZZZZZ";

ENDCASE;

ENDPROCESS;

ENDencoder_arch;

实验三：

注：

以下的AAA

（1）

（2）（3）（4）为课前做好的，但课上老师要求有了些变化，实际上机的代码在下面BBB中

AAA

（1）带异步复位的四位二进制减计数器

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYcount_1IS

PORT（

clk,reset:

INSTD_LOGIC;

OUTSTD_LOGIC_VECTOR（3DOWNTO0））;

ENDcount_1;

ARCHITECTUREaOFcount_1IS

SIGNALq_temp:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

PROCESS（clk,reset）

BEGIN

IFreset='0'THEN

q_temp<="1111";

ELSIFclk'EVENTANDclk='1'THEN

q_temp<=q_temp-1;

ENDIF;

ENDPROCESS;

q<=q_temp;

ENDa;

（2）带异步复位的8421码十进制计数器

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYcount_BCDIS

PORT（

clk,reset:

INSTD_LOGIC;

OUTSTD_LOGIC_VECTOR（3DOWNTO0））;

ENDcount_BCD;

ARCHITECTUREaOFcount_BCDIS

SIGNALq_temp:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

PROCESS（clk,reset）

BEGIN

IFreset='0'THEN

q_temp<="0000";

ELSIFclk'EVENTANDclk='1'THEN

IFq_temp="1001"THEN

q_temp<="0000";

ELSEq_temp<=q_temp+1;

ENDIF;

ENDPROCESS;

q<=q_temp;

ENDa;

（3）分频器

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYdiv_12IS

PORT（

clk:

INSTD_LOGIC;

clear:

INSTD_LOGIC;

clk_out:

OUTSTD_LOGIC）;

ENDdiv_12;

ARCHITECTUREaOFdiv_12IS

SIGNALtemp:

INTEGERRANGE0TO11;

BEGIN

p1:

PROCESS（clear,clk）

BEGIN

IFclear='0'THEN

temp<=0;

ELSIFclk'EVENTANDclk='1'THEN

IFtemp=11THEN

temp<=0;

ELSEtemp<=temp+1;

ENDIF;

ENDPROCESSp1;

p2:

PROCESS（temp）

BEGIN

IFtemp<6THEN

clk_out<='0';

ELSEclk_out<='1';

ENDIF;

ENDPROCESSp2;

ENDa;

（4）带异步复位的四位环形计数器

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYringIS

PORT（

clk,reset:

INSTD_LOGIC;

countout:

OUTSTD_LOGIC_VECTOR（3DOWNTO0））;

ENDring;

ARCHITECTUREbehaveOFringIS

SIGNALnextcount:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

PROCESS（clk,reset）--0001-0010-0100-1000-0001

BEGIN

IFreset='0'THENnextcount<="0001";

ELSIFclk'EVENTANDclk='1'THEN

CASEnextcountIS

WHEN"0001"=>nextcount<="0010";

WHEN"0010"=>nextcount<="0100";

WHEN"0100"=>nextcount<="1000";

WHENOTHERS=>nextcount<="0001";

ENDCASE;

ENDIF;

ENDPROCESS;

countout<=nextcount;

ENDbehave;

BBB

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYcount_BCDIS

PORT（

clk,reset:

INSTD_LOGIC;

OUTSTD_LOGIC_VECTOR（3DOWNTO0））;

ENDcount_BCD;

ARCHITECTUREaOFcount_BCDIS

SIGNALq_temp:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

PROCESS（clk,reset）

BEGIN

IFreset='1'THEN

q_temp<="0000";

ELSIFclk'EVENTANDclk='1'THEN

IFq_temp="1001"THEN

q_temp<="0000";

ELSEq_temp<=q_temp+1;

ENDIF;

ENDPROCESS;

q<=q_temp;

ENDa;

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYringIS

PORT（

clk,reset:

INSTD_LOGIC;

--clk_out:

outSTD_LOGIC;

countout:

OUTSTD_LOGIC_VECTOR（3DOWNTO0））;

ENDring;

ARCHITECTUREbehaveOFringIS

SIGNALnextcount:

STD_LOGIC_VECTOR（3DOWNTO0）;

SIGNALtemp:

STD_LOGIC;

BEGIN

p1:

PROCESS（clk）

VARIABLEcount:

integerrange0to25000000;

BEGIN

IF（clk'EVENTANDclk='1'）THEN

IF（count=25000000）THEN

count:

=0;

temp<=nottemp;

ELSEcount:

=count+1;

ENDIF;

ENDPROCESSp1;

--clk_out<=temp;

p2:

PROCESS（temp,reset）--0001-0010-0100-1000-0001

BEGIN

IFreset='1'THENnextcount<="0001";

ELSIFtemp'EVENTANDtemp='1'THEN

CASEnextcountIS

WHEN"0001"=>nextcount<="0010";

WHEN"0010"=>nextcount<="0100";

WHEN"0100"=>nextcount<="1000";

WHENOTHERS=>nextcount<="0001";

ENDCASE;

ENDIF;

ENDPROCESSp2;

countout<=nextcount;

ENDbehave;

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYdiv_12newIS

PORT（

clk:

INSTD_LOGIC;

clear:

INSTD_LOGIC;

clk_out:

OUTSTD_LOGIC）;

ENDdiv_12new;

ARCHITECTUREaOFdiv_12newIS

SIGNALtemp:

STD_LOGIC;

BEGIN

PROCESS（clear,clk）

VARIABLEcount:

integerrange0to5;

BEGIN

if（clear='1'）then

count:

=0;

ELSIF（clk'EVENTANDclk='1'）THEN

IF（count=5）THEN

count:

=0;

temp<=nottemp;

ELSEcount:

=count+1;

ENDIF;

ENDPROCESS;

clk_out<=temp;

ENDa;

实验四：

这个稍有难度，而且书上没有多少参考代码，仔细研究哦~

（1）数码管显示012345

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entitynixietube1is

port（clk:

instd_logic;

partout:

outstd_logic_vector（6downto0）;

catout:

outstd_logic_vector（5downto0））;

endnixietube1;

architectureaofnixietube1is

signalpart:

std_logic_vector（6downto0）;

signalcat:

std_logic_vector（5downto0）;

signaltempclk:

std_logic;

signalcount:

integerrange0to50000;

begin

p1:

process（clk）

begin

if（clk'eventandclk='1'）then

ifcount=50000then

count<=0;

tempclk<=nottempclk;

else

count<=count+1;

endif;

endprocessp1;

p2:

process（tempclk）

begin

if（tempclk'eventandtempclk='1'）then

casecatis

when"111110"=>cat<="011111";part<="1111110";--0

when"011111"=>cat<="101111";part<="0110000";--1

when"101111"=>cat<="110111";part<="1101101";--2

when"110111"=>cat<="111011";part<="1111001";--3

when"111011"=>cat<="111101";part<="0110011";--4

when"111101"=>cat<="111110";part<="1011011";--5

whenothers=>cat<="011111";part<="1111110";--0

endcase;

endif;

endprocessp2;

catout<=cat;

partout<=part;

enda;

（2）数码管滚动显示012345

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entityshiyan12new2is

port（clk:

instd_logic;

partout:

outstd_logic_vector（6downto0）;

catout:

outstd_logic_vector（5downto0））;

endshiyan12new2;

architectureaofshiyan12new2is

signalpart:

std_logic_vector（6downto0）;

signalcat:

std_logic_vector（5downto0）;

signalnumber:

std_logic_vector（5downto0）;

signaltempclk:

std_logic;--aclk（div1）

signalmove:

std_logic;--aclk（div2）

begin

p1:

process（clk）--div1（cat0-5）

variablecount:

integerrange0to50000:

=0;

begin

if（clk'eventandclk='1'）then

if（count=50000）then

count:

=0;

tempclk<=nottempclk;

else

count:

=count+1;

endif;

endprocessp1;

p2:

process（tempclk）

begin

iftempclk'eventandtempclk='1'then

casecatis

when"011111"=>cat<="101111";

when"101111"=>cat<="110111";

when"110111"=>cat<="111011";

when"111011"=>cat<="111101";

when"111101"=>cat<="111110";

whenothers=>cat<="011111";

endcase;

endif;

endprocessp2;

catout<=cat;

p3:

process（clk）--div2（onecatandchange）about1Hz

variablecount:

integerrange0to25000000:

=0;

begin

if（clk'eventandclk='1'）then

if（count=25000000）then

count:

=0;

move<=notmove;

else

count:

=count+1;

endif;

endprocessp3;

p4:

process（tempclk,move）--makenumbers

variablejudge1:

integerrange0to1:

=0;--1when"move"come

variablejudge2:

integerrange0to1:

=0;

begin

if（move'eventandmove='1'）then

judge1:

=1;

endif;

if（tempclk'eventandtempclk='1'）then

if（judge1=0）then--whenmovedonnotcome

casenumberis

when"011111"=>number<="101111";

when"101111"=>number<="110111";

when"110111"=>number<="111011";

when"111011"=>number<="111101";

when"111101"=>number<="111110";

whenothers=>numbe

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