用VHDL语言设计555压控振荡器测频率之欧阳体创编.docx
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用VHDL语言设计555压控振荡器测频率之欧阳体创编
实验五利用压控振荡器测量电压
时间:
2021.02.03
创作:
欧阳体
一、实验目的
(1)以555定时器为基础设计压控振荡器
(2)设计一个具有如下功能的简易频率计。
1.可以测量压控振荡器产生的频率,用4位数码管显示
2.测量结果直接用十进制数值显示
3.被测信号是压控振荡器产生的方波脉冲信号,根据设计的压控振荡器确定电压值
4.具有超量程警告(可以用LED灯显示)
二、实验设备与器材
(1)计算机:
QuartusⅡ16.0软件;
(2)硬件:
CycloneDE0-CVFPGA开发平台、555定时器、电阻、电容、可变电阻
三、利用Multisim搭建仿真电路
四、实验程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
--计数器
entitycnt10is
port(rst,fx,ena:
instd_logic;
cout:
outstd_logic;
outy:
outstd_logic_vector(3downto0));
endcnt10;
architecturebehvofcnt10is
begin
process(rst,ena,fx)
--定义变量
--<=是对信号赋值;而:
=是对变量进行赋值
variablecqi:
std_logic_vector(3downto0);
begin
--others=>'0'是对数组cqi所有元素赋值0
ifrst='1'thencqi:
=(others=>'0');
elsiffx'eventandfx='1'then
ifena='1'then
ifcqi<9then
cqi:
=cqi+1;cout<='0';
elsifcqi=9then
cqi:
=(others=>'0');
cout<='1';
endif;
elsifena='0'thencqi:
=(others=>'0');
endif;
endif;
outy<=cqi;
endprocess;
endbehv;
--4位10进计数器
libraryieee;
useieee.std_logic_1164.all;
entitycnt10_4is
port(fx,rst,ena,clk:
instd_logic;
d:
outstd_logic_vector(15downto0);
led_a:
outstd_logic);
endentity;
architectureoneofcnt10_4is
componentcnt10
port(rst,fx,ena:
instd_logic;
cout:
outstd_logic;
outy:
outstd_logic_vector(3downto0));
endcomponent;
componentled_hehe
port(
ena,clk:
instd_logic;
q:
outstd_logic);
endcomponent;
signale:
std_logic_vector(3downto0);
begin
--整体使用相同的rst和ena,fx作为进位使用。
u1:
cnt10portmap(fx=>fx,rst=>rst,ena=>ena,cout=>e(0),outy=>d(3downto0));
u2:
cnt10portmap(fx=>e(0),rst=>rst,ena=>ena,cout=>e
(1),outy=>d(7downto4));
u3:
cnt10portmap(fx=>e
(1),rst=>rst,ena=>ena,cout=>e
(2),outy=>d(11downto8));
u4:
cnt10portmap(fx=>e
(2),rst=>rst,ena=>ena,cout=>e(3),outy=>d(15downto12));
u5:
led_heheportmap(ena=>e(3),clk=>clk,q=>led_a);
endarchitectureone;
--16位锁存器latch=闩
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitylatch4is
port(d:
instd_logic_vector(15downto0);
ena,clk:
instd_logic;
q:
outstd_logic_vector(15downto0));
endlatch4;
architectureoneoflatch4is
begin
process(clk,ena,d)
variablecqi:
std_logic_vector(15downto0);
begin
ifena='0'thencqi:
=cqi;---ena=0锁存上次的数据
elsifclk'eventandclk='1'thencqi:
=d;---clk=1&&ena=1计入新数据
endif;
q<=cqi;
endprocess;
endone;
--报警ledhehe
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityled_heheis
port(
ena,clk:
instd_logic;
q:
outstd_logic);
endled_hehe;
architectureoneofled_heheis
begin
process(clk,ena)
variablecqi:
std_logic;
begin
ifena='0'thencqi:
=cqi;---ena=0锁存上次的数据
elsifclk'eventandclk='1'thencqi:
=notcqi;---clk=1&&ena=1计入新数据
endif;
q<=cqi;
endprocess;
endone;
--LED控制模块(数码管controller)
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityled_controlleris
port(d:
instd_logic_vector(3downto0);
a:
outstd_logic_vector(6downto0));
endled_controller;
architectureoneofled_controlleris
begin
process(d)
begin
casedis
when"0000"=>a<="1000000";when"0001"=>a<="1111001";
when"0010"=>a<="0100100";when"0011"=>a<="0110000";
when"0100"=>a<="0011001";when"0101"=>a<="0010010";
when"0110"=>a<="0000010";when"0111"=>a<="1111000";
when"1000"=>a<="0000000";when"1001"=>a<="0010000";
when"1010"=>a<="0001000";when"1011"=>a<="0000011";
when"1100"=>a<="1000110";when"1101"=>a<="0100001";
when"1110"=>a<="0000110";when"1111"=>a<="0001110";
whenothers=>null;
endcase;
endprocess;
end;
--控制模块(每隔一次clk,就翻转ena和rst)
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycontrolis
port(clk:
instd_logic;
rst,ena:
outstd_logic);
endcontrol;
architecturebehvofcontrolis
begin
process(clk)
variablecqi:
std_logic_vector(2downto0);
begin
ifclk'eventandclk='1'then
ifcqi<1thencqi:
=cqi+1;ena<='1';rst<='0';
elsifcqi=1then
cqi:
=(others=>'0');
ena<='0';rst<='1';
endif;
endif;
endprocess;
endbehv;
--时钟(1hz)发生器
libraryieee;
useieee.std_logic_1164.all;
entityfreq_divis
port(clk:
instd_logic;
clk_out:
outstd_logic);
endfreq_div;
architecturefwmoffreq_divis
constantm:
integer:
=25000;
signaltmp:
std_logic;
begin
process(clk,tmp)
variablecout:
integer:
=0;
begin
ifclk'eventandclk='1'then
cout:
=cout+1;
ifcout<=mthen
tmp<='0';
elsifcouttmp<='1';
elsecout:
=0;
endif;
endif;
endprocess;
clk_out<=tmp;
endfwm;
--总体例化语句:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
--clk是50hz的板载时钟信号,即参考信号,而fx才是测量的输入信号
entityvocis
port(clk:
instd_logic;
fx:
instd_logic;
ledout:
outstd_logic_vector(28downto0));---数码管7*4
endentity;
architectureoneofvocis
componentfreq_div
port(clk:
instd_logic;
clk_out:
outstd_logic);
endcomponent;
componentcontrol
port(clk:
instd_logic;
rst,ena:
outstd_logic);
endcomponent;
componentcnt10_4
port(clk,fx,rst,ena:
instd_logic;
d:
outstd_logic_vector(15downto0);
led_a:
outstd_logic);
endcomponent;
componentlatch4
port(d:
instd_logic_vector(15downto0);
ena,clk:
instd_logic;
q:
outstd_logic_vector(15downto0));
endcomponent;
componentled_controller
port(d:
instd_logic_vector(3downto0);
a:
outstd_logic_vector(6downto0));
endcomponent;
signalx,z:
std_logic;
signalg,h:
std_logic_vector(15downto0);
signalleds:
std_logic_vector(28downto0);
signalclk_base:
std_logic;
begin
u1:
freq_divportmap(clk=>clk,clk_out=>clk_base);
u2:
controlportmap(clk=>clk_base,ena=>x,rst=>z);
u3:
cnt10_4portmap(fx=>fx,rst=>z,ena=>x,d=>g,led_a=>leds(28),clk=>clk_base);
u4:
latch4portmap(clk=>clk_base,ena=>x,d=>g,q=>h);
u5:
led_controllerportmap(d(3downto0)=>h(3downto0),a(6downto0)=>leds(6downto0));
u6:
led_controllerportmap(d(3downto0)=>h(7downto4),a(6downto0)=>leds(13downto7));
u7:
led_controllerportmap(d(3downto0)=>h(11downto8),a(6downto0)=>leds(20downto14));
u8:
led_controllerportmap(d(3downto0)=>h(15downto12),a(6downto0)=>leds(27downto21));
ledout<=leds;
end;
--引脚配置说明:
--port(clk:
instd_logic;
--fx:
instd_logic;
--ledout:
outstd_logic_vector(27downto0));---数码管7*4clk
五、实验结果
1、搭建555实际电路
2、用示波器测量实际电路的频率和电压:
3、用已经下载了程序的开发板来测量实际电路的频率(由于开发板的数码管最后一个一直不稳定,所以把原本应该是最后一个的管脚绑到了第一个管脚,读频率的时候第一个数是个位,第二个数是千位,第三个数是百位,第四个数是十位;读出来的频率数乘以十就是单位为Hz的频率数)
时间:
2021.02.03
创作:
欧阳体