89c5单片机论文英文文献翻译.docx
《89c5单片机论文英文文献翻译.docx》由会员分享,可在线阅读,更多相关《89c5单片机论文英文文献翻译.docx(18页珍藏版)》请在冰豆网上搜索。
![89c5单片机论文英文文献翻译.docx](https://file1.bdocx.com/fileroot1/2023-2/6/204c8ea2-2005-470c-be5d-cdb1e6c85ce6/204c8ea2-2005-470c-be5d-cdb1e6c85ce61.gif)
89c5单片机论文英文文献翻译
英文原文
Description
TheAT89C51isalow-power,high-performanceCMOS8-bitmicrocomputerwith4KbytesofFlashProgrammableandErasableReadOnlyMemory(PEROM)and128bytesRAM.ThedeviceismanufacturedusingAtm-el’shighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandardMCS-51™instructionsetandpinout.Thechipcombinesaversatile8-bitCPUwithFlashonamonolithicchip,theAtm-elAT89C51isapowerfulmicrocomputerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplications.
Features:
•CompatiblewithMCS-51™Products
•4KBytesofIn-SystemReprogrammableFlashMemory
•Endurance:
1,000Write/EraseCycles
•FullyStaticOperation:
0Hzto24MHz
•Three-LevelProgramMemoryLock
•128x8-BitInternalRAM
•32ProgrammableI/OLines
•Two16-BitTimer/Counters
•SixInterruptSources
•ProgrammableSerialChannel
•LowPowerIdleandPowerDownModes
TheAT89C51providesthefollowingstandardfeatures:
4KbytesofFlash,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsystemtocontinuefunctioning.ThePowerDownModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.
BlockDiagram
PinDescription:
VCCSupplyvoltage.
GNDGround.
Port0
Port0isan8-bitopendrainbidirectionalI/Oport.AsanoutputporteachpincansinkeightTTLinputs.Whenisarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.
Port0mayalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalpull-ups.
Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringprogramverification.Externalpull-upsarerequiredduringprogramverification.
Port1
Port1isan8-bitbidirectionalI/Oportwithinternalpull-ups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.
Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.
Port2
Port2isan8-bitbidirectionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.
Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplicationitusesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.
Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.
Port3
Port3isan8-bitbidirectionalI/Oportwithinternalpull-ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepull-ups.
Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow:
Portpin
alternatefunctions
P3.0
Rad(serialinputport)
P3.1
TX(serialoutputport)
P3.2
^int0(externalinterrupt0)
P3.3
^int1(externalinterrupt1)
P3.4
t0(timer0externalinput)
P3.5
t1(timer1externalinput)
P3.6
^WR(externaldatamemorywritestrobe)
P3.7
^rd(externaldatamemoryreadstrobe)
Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.
RST
Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.
ALE/PROG
AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(PROG)duringFlashprogramming.
InnormaloperationALEisemittedataconstantrateof1/6theoscillatorfrequency,andmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternalDataMemory.
Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicro-controllerisinexternalexecutionmode.
PSEN
ProgramStoreEnableisthereadstrobetoexternalprogrammemory.
WhentheAT89C51isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.
EA/VPP
ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.
EAshouldbestrappedtoVCCforinternalprogramexecutions.
Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming,forpartsthatrequire12-voltVPP.
XTAL1
Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.
XTAL2
Outputfromtheinvertingoscillatoramplifier.
OscillatorCharacteristics
XTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator,asshowninFigure1.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdrivenasshowninFigure2.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.
IdleMode
Inidlemode,theCPUputsitselftosleepwhilealltheon-chipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.
Itshouldbenotedthatwhenidleisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecution,fromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.ToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyreset,theinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemory.
StatusofExternalPinsDuringIdleandPowerDownModes
mode
Programmemory
ALE
^pens
Port0
Port1
Port2
Port3
idle
internal
1
1
data
data
data
Data
Idle
External
1
1
float
Data
data
Data
Powerdown
Internal
0
0
Data
Data
Data
Data
Powerdown
External
0
0
float
data
Data
data
PowerDownMode
Inthepowerdownmodetheoscillatorisstopped,andtheinstructionthatinvokespowerdownisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepowerdownmodeisterminated.Theonlyexitfrompowerdownisahardwarereset.ResetredefinestheSF-Rsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.
ProgramMemoryLockBits
Onthechiparethreelockbitswhichcanbeleftunprogrammed(U)orcanbeprogrammed(P)toobtaintheadditionalfeatureslistedinthetablebelow:
LockBitProtectionModes:
Programlockbits
Protectiontype
Lb1
Lb2
Lb3
1
U
U
U
Noprogramlockfeatures
2
P
U
U
Moveinstructionsexecutedfromexternalprogrammemoryaredisablefromfetchingcodebytesfrominternalmemory,^eaissampledandlatchedonreset,andfurtherprogrammingoftheflashdisabled
3
P
P
U
Sameasmode2,alsoverifyisdisable.
4
P
P
P
Sameasmode3,alsoexternalexecutionisdisabled.
Whenlockbit1isprogrammed,thelogiclevelattheEApinissampledandlatchedduringreset.Ifthedeviceispoweredupwithoutareset,thelatchinitializestoarandomvalue,andholdsthatvalueuntilresetisactivated.ItisnecessarythatthelatchedvalueofEAbeinagreementwiththecurrentlogiclevelatthatpininorderforthedevicetofunctionproperly.
P89C51SpecialFunctionRegisters:
SYMBOL
DESCRIPTION
BYTES
ADDRESS
BITADDRESS,SYMBOL
ACC
Accumulator
E0H
E7E6E5E4E3E2E1E0
ACC.7ACC.6ACC.5ACC.4ACC.3ACC.2ACC.1ACC.0
B*
Bregister
F0H
F7F6F5F4F3F2F1F0
B.7B.6B.5B.4B.3B.2B.1B.0
DPH
DataPointerHigh
83H
DPL
DataPointerLow
82H
IE
InterruptEnable
A8H
AF–-–-ACABAAA9A8
EAESET1EX1ET0EX0
IP*
InterruptPriority