89c5单片机论文英文文献翻译.docx

1、89c5单片机论文英文文献翻译英文原文DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atm-els high density nonvolatile memory technology and is compatible with

2、the industry standard MCS-51 instruction set and pin out. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atm-el AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features: Compatible wi

3、th MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-Level Program Memory Lock 128 x 8-Bit Internal RAM 32 Programmable I/O Lines Two 16-Bit Timer/Counters Six Interrupt Sources Programmable Serial Chann

4、el Low Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, th

5、e AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM conten

6、ts but freezes the oscillator disabling all other chip functions until the next hardware reset.Block DiagramPin Description:VCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pi

7、ns, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming, and outputs the

8、code bytes during program verification. External pull-ups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the interna

9、l pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port wit

10、h internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pu

11、ll-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bi

12、t addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers

13、can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various spec

14、ial features of the AT89C51 as listed below:Port pinalternate functionsP3.0Rad (serial input port)P3.1TX (serial output port)P3.2int0 (external interrupt0)P3.3int1 (external interrupt1)P3.4t0 (timer0 external input)P3.5t1 (timer1 external input)P3.6 WR (external data memory write strobe)P3.7rd (exte

15、rnal data memory read strobe)Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address

16、 during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped

17、during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the micro-control

18、ler is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memo

19、ry.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for inte

20、rnal program executions. This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplif

21、ier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source,

22、 XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifica

23、tions must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by an

24、y enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to inte

25、rnal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Status of E

26、xternal Pins During Idle and Power Down ModesmodeProgram memoryALEpensPort0 Port1Port2Port3idleinternal11datadatadataDataIdleExternal11floatDatadataDataPower downInternal00DataDataDataDataPower downExternal 00floatdataDatadataPower Down ModeIn the power down mode the oscillator is stopped, and the i

27、nstruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SF-Rs but does not change the on-chip RAM. The reset

28、 should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additio

29、nal features listed in the table below: Lock Bit Protection Modes：Program lock bitsProtection typeLb1 Lb2Lb31UUUNo program lock features2PUUMove instructions executed from external program memory are disable from fetching code bytes from internal memory, ea is sampled and latched on reset, and furth

30、er programming of the flash disabled3PPUSame as mode 2, also verify is disable.4PPPSame as mode 3, also external execution is disabled.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes

31、to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.P89C51 Special Function Registers：SYMBOLDESCRIPTIONBYTESADDRESSBIT ADDRESS, SYMBOL ACCAccumulatorE0HE7 E6 E5 E4 E3 E2 E1 E0ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 B*B registerF0HF7 F6 F5 F4 F3 F2 F1 F0B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0DPHData Pointer High83HDPLData Pointer Low82HIEInterrupt EnableA8HAF - - AC AB AA A9 A8EA ES ET1 EX1 ET0 EX0IP*Interrupt Priority