EDA数字时钟设计说明.docx
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EDA数字时钟设计说明
Quartus数字时钟设计
1.设计功能
1.可以快速设置时钟起始值;
2.在59分50秒时开始报时,七声低音,一声高音,报完刚好整点。
二.功能实现
1.顶层设计(采用BDF文件图形设计,文件名:
timer.bdf)
2.秒计时器模块设计
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitysecond1is
port(clk1s:
instd_logic;
reset:
instd_logic;
sec2,sec1:
bufferstd_logic_vector(3downto0);--秒的十位和个位
seco:
outstd_logic);--秒计时器的进位输出
end;
architectureAofsecond1is
begin
process(clk1s,reset)
begin
ifreset='0'then
sec2<="0000";sec1<="0000";--清零秒计时器
seco<='0';
elsifclk1s'eventandclk1s='1'then
if(sec1="1001"andsec2="0101")then
sec2<="0000";sec1<="0000";--在59秒时回零
seco<='1';--进位
elsif(sec1="1001")then
sec1<="0000";
sec2<=sec2+1;
seco<='0';
else
sec1<=sec1+1;
seco<='0';
endif;
endif;
endprocess;
end;
3.分计时器模块设计
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityminute1is
port(clkm,clk1s,setm:
instd_logic;--秒进位输入,1HZ校分时钟输入信号,校分控制信号
min2,min1:
bufferstd_logic_vector(3downto0);--分计时器的十位和个位
minco:
outstd_logic);
end;
architectureAofminute1is
signalclkx:
std_logic;
begin
Pclkm:
process(clkm,clk1s,setm)
begin--根据是否校分选择计时时钟
ifsetm='1'thenclkx<=clk1s;--利用clk1s信号对分的初值进行快速设置
elseclkx<=clkm;--利用秒的进位信号正常计时
endif;
endprocess;
Pcontm:
process(clkx)
begin
ifclkx'eventandclkx='1'then
if(min1="1001"andmin2="0101")then
min1<="0000";min2<="0000";minco<='1';--59分时回零并进位
elsif(min1="1001")then
min1<="0000";min2<=min2+1;
minco<='0';
else
min1<=min1+1;minco<='0';
endif;
endif;
endprocess;
end;
4.时计时器模块设计
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityhour1is
port(clkh,clk1s,seth:
instd_logic;
hou2,hou1:
bufferstd_logic_vector(3downto0));--时的十位和个位
end;
architectureAofhour1is
signalclky:
std_logic;
begin
Pclkh:
process(clkh,clk1s,seth)
Begin--根据是否校时选择计时时钟
ifseth='1'thenclky<=clk1s;--利用clk1s信号对时的初值进行快速设置
elseclky<=clkh;--利用分的进位信号正常计时
endif;
endprocess;
Pconth:
process(clky)
begin
ifclky'eventandclky='1'then
if(hou1="0011"andhou2="0010")then
hou1<="0000";hou2<="0000";--23时回零
elsif(hou1="1001")then
hou1<="0000";
hou2<=hou2+1;
else
hou1<=hou1+1;
endif;
endif;
endprocess;
end;
5.报时模块设计
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityalarm1is
port(clk1s,clk500,clk1k:
instd_logic;
sec2,sec1,min2,min1:
instd_logic_vector(3downto0);
alarm:
outstd_logic);
end;
architectureAofalarm1is
begin
process(clk1s)
variableflag500:
std_logic;variableflag1k:
std_logic;
begin
ifclk1s'eventandclk1s='1'then
if(min1="1001"andmin2="0101"andsec2="0101")then--59分50秒时开始报时
casesec1is
when"0000"=>flag500:
='1';
when"0010"=>flag500:
='1';
when"0100"=>flag500:
='1';
when"0110"=>flag500:
='1';
when"0111"=>flag500:
='1';
when"1000"=>flag500:
='1';
when"1001"=>flag500:
='1';--50,52,54,56,58,59秒时低频率报时
whenothers=>flag500:
='0';flag1k:
='0';
endcase;
elseflag500:
='0';flag1k:
='0';
endif;
if(min1="0000"andmin2="0000"andsec1="0000"andsec2="0000")then
flag1k:
='1';--整点时高频率报时
endif;
endif;
ifflag500='1'thenalarm<=clk500;
elsifflag1k='1'thenalarm<=clk1k;
elsealarm<='0';
endif;
endprocess;
end;
三.仿真结果
1.秒计时器仿真结果
2.分计时器仿真结果
3.时计时器仿真结果
4.报时模块仿真结果
5.timer仿真结果
四.疑惑
1.仿真结果中,由于输出信号向量(比如sec1(0),sec1
(1),sec1
(2),sec1(3))变化的不同时,使得组合后的sec1,sec2,min1,min2均出现毛刺,尝试了引入中间变量,中间信号的方法,都不能解决问题。
怎么办才好?