VHDL程序集锦.docx
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VHDL程序集锦
组合逻辑：
最高优先级编码器
--HighestPriorityEncoder--downloadfrom&
LIBRARYieee;
USEieee.std_logic_1164.ALL;
entitypriorityis
port（I:
inbit_vector（7downto0）;--inputstobeprioritisedA:
outbit_vector（2downto0）;--encodedoutputGS:
outbit）;--groupsignaloutputendpriority;
architecturev1ofpriorityisbegin
process（I）
begin
GS<='1';--setdefaultoutputs
A<="000";
ifI（7）='1'then
A<="111"
elsifI（6）='1'thenA<="110";
elsifI（5）='1'thenA<="101";
elsifI（4）='1'then
A<="100";elsifI（3）='1'then
A<="011";elsifI
（2）='1'then
A<="010";elsifI
（1）='1'then
A<="001";
elsifI（0）='1'thenA<="000";
else
GS<='0';endif;endprocess;
endv1;
8位相等比较器
--8-bitIdentityComparator
--uses1993stdVHDL
--downloadfrom&
libraryIEEE;
useIEEE.Std_logic_1164.all;entityHCT688is
port（Q,P:
instd_logic_vector（7downto0）;
GBAR:
instd_logic;PEQ:
outstd_logic）;endHCT688;
architectureVER1ofHCT688is
begin
PEQ<='0'when（（To_X01（P）=To_X01（Q））and（GBAR='0'））else'1';endVER1;
三人表决器（三种不同的描述方式）
--Three-inputMajorityVoter
--Theentitydeclarationisfollowedbythreealternativearchitectureswhichachievethesamefunctionalityindifferentways.
--downloadfrom:
&
ENTITYmajIS
PORT（a,b,c:
INBIT;m:
OUTBIT）;
ENDmaj;
--Dataflowstylearchitecture
ARCHITECTUREconcurrentOFmajIS
BEGIN
--selectedsignalassignmentstatement（concurrent）
WITHa&b&cSELECT
m<='1'WHEN"110"|"101"|"011"|"111",'0'WHENOTHERS;
ENDconcurrent;
--Structuralstylearchitecture
ARCHITECTUREstructureOFmajIS
--declarecomponentsusedinarchitecture
COMPONENTand2PORT（in1,in2:
INBIT;out1:
OUTBIT）;
ENDCOMPONENT;
COMPONENTor3PORT（in1,in2,in3:
INBIT;out1:
OUTBIT）;
ENDCOMPONENT;
--declarelocalsignals
SIGNALw1,w2,w3:
BIT;
BEGIN
--componentinstantiationstatements.
--portsofcomponentaremappedtosignals
--withinarchitecturebyposition.
gate1:
and2PORTMAP（a,b,w1）;
gate2:
and2PORTMAP（b,c,w2）;
gate3:
and2PORTMAP（a,c,w3）;gate4:
or3PORTMAP（w1,w2,w3,m）;
ENDstructure;
--Behaviouralstylearchitectureusingalook-uptableARCHITECTUREusing_tableOFmajISBEGIN
PROCESS（a,b,c）
CONSTANTlookuptable:
BIT_VECTOR（0TO7）:
="00010111";VARIABLEindex:
NATURAL;
BEGIN
index:
=0;--indexmustbeclearedeachtimeprocessexecutesIFa='1'THENindex:
=index+1;ENDIF;
IFb='1'THENindex:
=index+2;ENDIF;
IFc='1'THENindex:
=index+4;ENDIF;m<=lookuptable（index）;
ENDPROCESS;
ENDusing_table;
加法器描述
--AVarietyofAdderStyles--downloadfrom:
&--Single-bitadderlibraryIEEE;
useIEEE.std_logic_1164.all;
entityadderis
port（a:
instd_logic;b:
instd_logic;cin:
instd_logic;sum:
outstd_logic;cout:
outstd_logic）;
endadder;
--descriptionofadderusingconcurrentsignalassignmentsarchitecturertlofadderis
begin
sum<=（axorb）xorcin;
cout<=（aandb）or（cinanda）or（cinandb）;
endrtl;
--descriptionofadderusingcomponentinstantiationstatements--MiscellaneousLogicGatesusework.gates.all;
architecturestructuralofadderissignalxor1_out,and1_out,and2_out,or1_out:
std_logic;
begin
xor1:
xorgportmap（
in1=>a,
in2=>b,
out1=>xor1_out）;
xor2:
xorgportmap（
in1=>xor1_out,
in2=>cin,out1=>sum）;
and1:
andgportmap（
in1=>a,
in2=>b,
out1=>and1_out）;
or1:
orgportmap（
in1=>a,
in2=>b,
out1=>or1_out）;
and2:
andgportmap（
in1=>cin,
in2=>or1_out,out1=>and2_out）;
or2:
orgportmap（
in1=>and1_out,
in2=>and2_out,
out1=>cout）;
endstructural;
--N-bitadder--ThewidthoftheadderisdeterminedbygenericNlibraryIEEE;
useIEEE.std_logic_1164.all;
entityadderNis
generic（N:
integer:
=16）;
port（a:
instd_logic_vector（Ndownto1）;b:
instd_logic_vector（Ndownto1）;cin:
instd_logic;
sum:
outstd_logic_vector（Ndownto1）;
cout:
outstd_logic）;
endadderN;
--structuralimplementationoftheN-bitadderarchitecturestructuralofadderNiscomponentadder
port（a:
instd_logic;b:
instd_logic;cin:
instd_logic;sum:
outstd_logic;cout:
outstd_logic）;
endcomponent;
signalcarry:
std_logic_vector（0toN）;
begin
carry（0）<=cin;
cout<=carry（N）;
--instantiateasingle-bitadderNtimes
gen:
forIin1toNgenerate
add:
adderportmap（
a=>a（I）,
b=>b（I）,
cin=>carry（I-1）,sum=>sum（I）,cout=>carry（I））;
endgenerate;
endstructural;
--behavioralimplementationoftheN-bitadderarchitecturebehavioralofadderNisbegin
p1:
process（a,b,cin）variablevsum:
std_logic_vector（Ndownto1）;variablecarry:
std_logic;
begin
carry:
=cin;
foriin1toNloop
vsum（i）:
=（a（i）xorb（i））xorcarry;
carry:
=（a（i）andb（i））or（carryand（a（i）orb（i）））;endloop;
sum<=vsum;
cout<=carry;
endprocessp1;endbehavioral;
8位总线收发器：
74245（注2）
--OctalBusTransceiver
--Thisexampleshowstheuseofthehighimpedanceliteral'Z'providedbystd_logic.
--Theaggregate'（others=>'Z'）'meansallofthebitsofBmustbeforcedto'Z'.
--PortsAandBmustberesolvedforthismodeltoworkcorrectly（hencestd_logicratherthanstd_ulogic）.
--downloadfrom:
&
libraryIEEE;
useIEEE.Std_logic_1164.all;
entityHCT245is
port（A,B:
inoutstd_logic_vector（7downto0）;
DIR,GBAR:
instd_logic）;
endHCT245;
architectureVER1ofHCT245is
begin
A<=Bwhen（GBAR='0'）and（DIR='0'）else（others=>'Z'）;
B<=Awhen（GBAR='0'）and（DIR='1'）else（others=>'Z'）;endVER1;
地址译码（form68008）
--M68008AddressDecoder
--Addressdecoderforthem68008
--asbarmustbe'0'toenableanyoutput
--csbar（0）:
X"00000"toX"01FFF"
--csbar
（1）:
X"40000"toX"43FFF"
--csbar
（2）:
X"08000"toX"0AFFF"
--csbar（3）:
X"E0000"toX"E01FF"
--downloadfrom&libraryieee;
useieee.std_logic_1164.all;
entityaddrdecisport（
asbar:
instd_logic;
address:
instd_logic_vector（19downto0）;
csbar:
outstd_logic_vector（3downto0））;
endentityaddrdec;
architecturev1ofaddrdecisbegin
csbar（0）<='0'when（（asbar='0'）and（（address>=X"00000"）and（address<=X"01FFF"）））else'1';
csbar
（1）<='0'when
（（asbar='0'）and
（（address>=X"40000"）and（address<=X"43FFF"）））else'1';
csbar
（2）<='0'when
（（asbar='0'）and
（（address>=X"08000"）and（address<=X"0AFFF"）））else'1';
csbar（3）<='0'when（（asbar='0'）and（（address>=X"E0000"）and（address<=X"E01FF"）））else'1';
endarchitecturev1;
多路选择器（使用select语句）
--Multiplexer16-to-4usingif-then-elsif-elseStatement--downloadfrom&libraryieee;
useieee.std_logic_1164.all;
entitymuxisport（
a,b,c,d:
s:
instd_logic_vector（3downto0）;instd_logic_vector（1downto0）;
x:
outstd_logic_vector（3downto0））;
endmux;
architecturearchmuxofmuxisbegin
mux4_1:
process（a,b,c,d）begin
ifs="00"then
x<=a;elsifs="01"then
x<=b;elsifs="10"then
x<=c;else
x<=d;endif;endprocessmux4_1;
endarchmux;
LED七段译码
--DESCRIPTION:
BINtosevensegmentsconverter--segmentencoding
--a
+---+
f||b
+---+<-ge||c
+---+
--d
:
high
:
low
--Enable（EN）active
--Outputs（data_out）active
--Downloadfrom:
libraryIEEE;
useIEEE.std_logic_1164.all;
entitybin27segis
port（
data_in:
instd_logic_vector（3downto0）;EN:
instd_logic;
data_out:
outstd_logic_vector（6downto0））;
endentity;
architecturebin27seg_archofbin27segisbegin
process（data_in,EN）
begin
data_out<=（others=>'1'）;
ifEN='1'thencasedata_inis
when"0000"=>data_out<="1000000";--0when"0001"=>data_out<="1111001";--1when"0010"=>data_out<="0100100";--2when"0011"=>data_out<="0110000";--3when"0100"=>data_out<="0011001";--4when"0101"=>data_out<="0010010";--5when"0110"=>data_out<="0000011";--6when"0111"=>data_out<="1111000";--7when"1000"=>data_out<="0000000";--8when"1001"=>data_out<="0011000";--9when"1010"=>data_out<="0001000";--Awhen"1011"=>data_out<="0000011";--bwhen"1100"=>data_out<="0100111";--cwhen"1101"=>data_out<="0100001";--dwhen"1110"=>data_out<="0000110";--Ewhen"1111"=>data_out<="0001110";--Fwhenothers=>NULL;
endcase;
endif;
endprocess;
endarchitecture;
多路选择器（使用if－else语句）
--Multiplexer16-to-4usingif-then-elsif-elseStatement--downloadfrom&libraryieee;
useieee.std_logic_1164.all;
entitymuxisport（
a,b,c,d:
s:
instd_logic_vector（3downto0）;instd_logic_vector（1downto0）;
x:
outstd_logic_vector（3downto0））;
endmux;
architecturearchmuxofmuxisbegin
mux4_1:
process（a,b,c,d）begin
ifs="00"then
x<=a;elsifs="01"then
x<=b;elsifs="10"then
x<=c;else
x<=d;endif;endprocessmux4_1;
endarchmux;
双2－4译码器：
74139
--Dual2-to-4Decoder
--Asetofconditionalsignalassignmentsmodeladual2-to-4decoder
--uses1993stdVHDL
--downloadfrom:
&
libraryIEEE;
useIEEE.Std_logic_1164.all;
entityHCT139isport（A2,B2,G2BAR,A1,B1,G1BAR:
instd_logic;
Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:
outstd_logic）;endHCT139;
architectureVER1ofHCT139is
begin
Y10<='0'when（B1='0'）and（（A1='0'）and（G1BAR='0'））else'1';
Y11<='0'when（B1='0'）and（（A1='1'）and（G1BAR='0'））else'1';
Y12<='0'when（B1='1'）and（（A1='0'）and（G1BAR='0'））else'1';
Y13<='0'when（B1='1'）and（（A1='1'）and（G1BAR='0'）
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