VHDL程序集锦.docx

1、VHDL程序集锦组合逻辑： 最高优先级编码器- Highest Priority Encoder - download from &LIBRARY ieee;USE ieee.std_logic_1164.ALL;entity priority isport(I : in bit_vector(7 downto 0); -inputs to be prioritised A : out bit_vector(2 downto 0); -encoded output GS : out bit); -group signal output end priority;architecture v1

2、of priority is beginprocess(I)beginGS = 1; -set default outputsA = 000;if I(7) = 1 thenA = 111elsif I(6) = 1 then A = 110;elsif I(5) = 1 then A = 101;elsif I(4) = 1 thenA = 100; elsif I(3) = 1 thenA = 011; elsif I(2) = 1 thenA = 010; elsif I(1) = 1 thenA = 001;elsif I(0) = 1 then A = 000;elseGS = 0;

3、 end if; end process;end v1;8位相等比较器- 8-bit Identity Comparator- uses 1993 std VHDL- download from &library IEEE;use IEEE.Std_logic_1164.all; entity HCT688 isport(Q, P : in std_logic_vector(7 downto 0);GBAR : in std_logic; PEQ : out std_logic); end HCT688;architecture VER1 of HCT688 isbeginPEQ = 0 wh

4、en (To_X01(P) = To_X01(Q) and (GBAR = 0) else 1; end VER1;三人表决器(三种不同的描述方式)- Three-input Majority Voter- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.- download from: &ENTITY maj ISPORT(a,b,c : IN BIT; m : OUT BIT);END ma

5、j;-Dataflow style architectureARCHITECTURE concurrent OF maj ISBEGIN-selected signal assignment statement (concurrent)WITH a&b&c SELECTm = 1 WHEN 110|101|011|111,0 WHEN OTHERS;END concurrent;-Structural style architectureARCHITECTURE structure OF maj IS-declare components used in architectureCOMPONE

6、NT and2 PORT(in1, in2 : IN BIT; out1 : OUT BIT);END COMPONENT;COMPONENT or3 PORT(in1, in2, in3 : IN BIT; out1 : OUT BIT);END COMPONENT;-declare local signalsSIGNAL w1, w2, w3 : BIT;BEGIN-component instantiation statements.-ports of component are mapped to signals-within architecture by position.gate

7、1 : and2 PORT MAP (a, b, w1);gate2 : and2 PORT MAP (b, c, w2);gate3 : and2 PORT MAP (a, c, w3); gate4 : or3 PORT MAP (w1, w2, w3, m);END structure;-Behavioural style architecture using a look-up table ARCHITECTURE using_table OF maj IS BEGINPROCESS(a,b,c)CONSTANT lookuptable : BIT_VECTOR(0 TO 7) :=

8、00010111; VARIABLE index : NATURAL;BEGINindex := 0; -index must be cleared each time process executes IF a = 1 THEN index := index + 1; END IF;IF b = 1 THEN index := index + 2; END IF;IF c = 1 THEN index := index + 4; END IF; m = lookuptable(index);END PROCESS;END using_table;加法器描述- A Variety of Add

9、er Styles - download from: & - Single-bit adder library IEEE;use IEEE.std_logic_1164.all;entity adder isport (a : in std_logic; b : in std_logic; cin : in std_logic; sum : out std_logic; cout : out std_logic);end adder;- description of adder using concurrent signal assignments architecture rtl of ad

10、der isbeginsum = (a xor b) xor cin;cout a,in2 = b,out1 = xor1_out);xor2: xorg port map(in1 = xor1_out,in2 = cin, out1 = sum);and1: andg port map(in1 = a,in2 = b,out1 = and1_out);or1: org port map(in1 = a,in2 = b,out1 = or1_out);and2: andg port map(in1 = cin,in2 = or1_out, out1 = and2_out);or2: org p

11、ort map(in1 = and1_out,in2 = and2_out,out1 = cout);end structural;- N-bit adder - The width of the adder is determined by generic N library IEEE;use IEEE.std_logic_1164.all;entity adderN isgeneric(N : integer := 16);port (a : in std_logic_vector(N downto 1); b : in std_logic_vector(N downto 1); cin

12、: in std_logic;sum : out std_logic_vector(N downto 1);cout : out std_logic);end adderN;- structural implementation of the N-bit adder architecture structural of adderN is component adderport (a : in std_logic; b : in std_logic; cin : in std_logic; sum : out std_logic; cout : out std_logic);end compo

13、nent;signal carry : std_logic_vector(0 to N);begincarry(0) = cin;cout a(I),b = b(I),cin = carry(I - 1), sum = sum(I), cout = carry(I);end generate;end structural;- behavioral implementation of the N-bit adder architecture behavioral of adderN is beginp1: process(a, b, cin) variable vsum : std_logic_

14、vector(N downto 1); variable carry : std_logic;begincarry := cin;for i in 1 to N loopvsum(i) := (a(i) xor b(i) xor carry;carry := (a(i) and b(i) or (carry and (a(i) or b(i); end loop;sum = vsum;cout = carry;end process p1; end behavioral;8 位总线收发器： 74245 (注 2 )- Octal Bus Transceiver- This example sh

15、ows the use of the high impedance literal Z provided by std_logic.- The aggregate (others = Z) means all of the bits of B must be forced to Z.- Ports A and B must be resolved for this model to work correctly (hence std_logic rather than std_ulogic).- download from: &library IEEE;use IEEE.Std_logic_1

16、164.all;entity HCT245 isport(A, B : inout std_logic_vector(7 downto 0);DIR, GBAR : in std_logic);end HCT245;architecture VER1 of HCT245 isbeginA Z);B Z); end VER1;地址译码( for m68008 )- M68008 Address Decoder- Address decoder for the m68008- asbar must be 0 to enable any output- csbar(0) : X00000 to X0

17、1FFF- csbar(1) : X40000 to X43FFF- csbar(2) : X08000 to X0AFFF- csbar(3) : XE0000 to XE01FF- download from & library ieee;use ieee.std_logic_1164.all;entity addrdec is port(asbar : in std_logic;address : in std_logic_vector(19 downto 0);csbar : out std_logic_vector(3 downto 0) );end entity addrdec;a

18、rchitecture v1 of addrdec is begincsbar(0) = X00000) and (address = X01FFF) else 1;csbar(1) = X40000) and (address = X43FFF) else 1;csbar(2) = X08000) and (address = X0AFFF) else 1;csbar(3) = XE0000) and (address = XE01FF) else 1;end architecture v1; 多路选择器(使用 select 语句)- Multiplexer 16-to-4 using if

19、-then-elsif-else Statement - download from & library ieee;use ieee.std_logic_1164.all;entity mux is port(a, b, c, d: s:in std_logic_vector(3 downto 0); in std_logic_vector(1 downto 0);x:out std_logic_vector(3 downto 0);end mux;architecture archmux of mux is beginmux4_1: process (a, b, c, d) beginif

20、s = 00 thenx = a; elsif s = 01 thenx = b; elsif s = 10 thenx = c; elsex = d; end if; end process mux4_1;end archmux;LED七段译码- DESCRIPTION : BIN to seven segments converter - segment encoding- a+-+f | | b+-+ - g e | | c+-+- d: high: low- Enable (EN) active- Outputs (data_out) active- Download from : l

21、ibrary IEEE;use IEEE.std_logic_1164.all;entity bin27seg isport (data_in : in std_logic_vector (3 downto 0); EN : in std_logic;data_out : out std_logic_vector (6 downto 0) );end entity;architecture bin27seg_arch of bin27seg is beginprocess(data_in, EN)begindata_out 1);if EN=1 then case data_in iswhen

22、 0000 = data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out NULL;end case;end if;end process;end architecture;多路选择器(使用 if else 语句)- Multiplexer 16-to-4 using if-then-elsif-else Statement - download from & lib

23、rary ieee;use ieee.std_logic_1164.all;entity mux is port(a, b, c, d: s:in std_logic_vector(3 downto 0); in std_logic_vector(1 downto 0);x:out std_logic_vector(3 downto 0);end mux;architecture archmux of mux is beginmux4_1: process (a, b, c, d) beginif s = 00 thenx = a; elsif s = 01 thenx = b; elsif

24、s = 10 thenx = c; elsex = d; end if; end process mux4_1;end archmux;双 2 4 译码器： 74139- Dual 2-to-4 Decoder- A set of conditional signal assignments model a dual 2-to-4 decoder- uses 1993 std VHDL- download from: &library IEEE;use IEEE.Std_logic_1164.all;entity HCT139 is port(A2, B2, G2BAR, A1, B1, G1

25、BAR : in std_logic;Y20, Y21, Y22, Y23, Y10, Y11, Y12, Y13 : out std_logic); end HCT139;architecture VER1 of HCT139 isbeginY10 = 0 when (B1 = 0) and (A1 = 0) and (G1BAR = 0) else 1;Y11 = 0 when (B1 = 0) and (A1 = 1) and (G1BAR = 0) else 1;Y12 = 0 when (B1 = 1) and (A1 = 0) and (G1BAR = 0) else 1;Y13 = 0 when (B1 = 1) and (A1 = 1) and (G1BAR = 0)