DC Design Compiler 综合脚本命令及参考模板.docx

DC Design Compiler 综合脚本命令及参考模板.docx

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DCDesignCompiler综合脚本命令及参考模板

DCDesignCompiler综合脚本命令及参考模板

DesignCompiler综合脚本

常用命令和模板

参照自己的设计，以及自己的工艺信息，适当修改下面的

Constraints和RunScript等的脚本，添加一些相关的约束语句，

就可以运行了

详细的命令请参照DC的官方UserGuide等相关资料。

InvokingDesignCompiler

Unix%design_vision#InteractiveGUI,WLMmodeUnix%design_vision–topographical#InteractiveGUI,Topographicalmode

Unix%dc_shell-t#Interactiveshell,WLMmodeUnix%dc_shell-t–topographical#Interactiveshell,Topographicalmode

Unix%dc_shell-t–fRUN.tcl|tee–imy.log#Batchmode

.synopsys_dc.setup

setsearch_path“$search_pathlibsconsunmappedrtl”

setsynthetic_librarydw_foundation.sldb

settarget_library65nm.db

setlink_library“*$target_library$synthetic_libraryIP.db”

setsymbol_library65nm.sdb

define_design_libWORK–path./work

set_svf

set_vsdc

historykeep200

setsh_enable_page_modefalse

setcache_write.

setcache_read$cache_write

suppress_message{LINT-28LINT-32LINT-33UID-401}setalib_library_analysis_path[get_unix_variableHOME]aliashhistory

aliasrc“report_constraint-all_violators”

TCLCommandsandConstructs

setPER2.0#Defineavariableanditsvalueecho$PER#Variablesubstitution,2.0

setMARG0.95

expr$PER*$MARG#expr:

*,/,+,-,>,<,=,<=,>=

setpci_ports[get_portsA]#Imbeddedcommandsetpci_ports[get_ports“Y?

?

MZ*”]#Wildcards

echo“EffctvP=\#Softquotes,1.9

[expr$PERIOD*$MARGIN]”

echo{EffctvP=\#Hardquotes

[expr$PERIOD*$MARGIN]}#,EffctvP=[expr$PER*$MARG]#Commentline

setCOMMENTin_line;#In-linecommentsetMY_DESIGNS{B1.v...B26.v}#foreachloopforeachDESIGN$MY_DESIGNS{

read_verilog$DESIGN

}

for{seti1}{$i<27}{incri}{#forloop

read_verilogBLOCK_$i.v

}

HelpfulUNIX-likeDC-shellcommands

pwd

cd

ls

history

!

!

!

7

!

report

sh

printenv

get_unix_variableARCH

Constraints

reset_design

set_max_area0

create_clock-period2–nameMain_Clk[get_portsClk1]

create_clock–period2.5–waveform{23.5}[get_portsClk2]create_clock–period3.5–nameV_Clk;#VIRTUALclock

set_clock_uncertainty–setup0.14[get_clocks*]

set_clock_uncertainty–setup0.21–from[get_clocksMain_Clk]–to[get_clocksClk2]set_clock_latency–max0.6[get_clocksMain_Clk]

set_clock_latency–source–max0.3[get_clocksMain_Clk]set_clock_transition0.08[get_clocksMain_Clk]set_input_delay-max0.6-clockMain_Clk[all_inputs]set_input_delay–max0.3–clockClk2–clock_fall–add_delay[get_ports“BE”]

set_input_delay-max0.5-clock–network_latency_includedV_Clk[get_ports“ACF”]

set_output_delay-max0.8-clock–source_latency_includedMain_Clk[all_outputs]

set_output_delay-max1.1-clockV_Clk[get_ports“OUT2OUT7]

set_max_capacitance1.2[all_inputs]

set_load0.080[all_outputs]

set_load[expr[load_ofslow_proc/NAND2_3/A]*4][get_portsOUT3]

set_load0.12[all_inputs]

set_input_transition0.12[remove_from_collection[all_inputs][get_portsB]]

set_driving_cell–lib_cellFD1–pinQ[get_portsB]

set_operating_conditions–maxWCCOM

setauto_wire_load_selectionfalse

set_wire_load_model–name1.6MGates

set_wire_load_modeenclosed

set_wire_load_model–name200KGates[get_designs“SUB1SUB2”]

set_wire_load_model–name3.2MGates[get_portsIN_A]set_port_fanout_number8[get_portsIN_A]set_false_path-from[get_clocksAsynch_CLKA]-to[get_clocksAsynch_CLKB]

set_multicycle_path–setup4–from–fromA_reg-throughU_Mult/Out–toB_reg

set_multicycle_path–hold3–from–fromA_reg-throughU_Mult/Out–toB_reg

set_isolate_ports–typeinverter[all_outputs]

set_ideal_network[get_portsreset*select*]set_ideal_network[get_pinsFF_SET_reg/Q]set_ideal_network–no_propagate[get_netsCTRL]

set_ideal_latency1.4[get_portsreset*select*]set_ideal_transition0.5[get_pinsFF_SET_reg/Q]set_scan_configuration-style

CheckingandRemovingConstraintsandDirectives

report_clock;report_clock-skew

report_design

report_port–verbose

report_wire_load

report_path_groups

report_timing_requirements（–ignored）report_auto_ungroupreport_isolate_portswrite_script–outputcheck_timing

reset_path–fromFF1_reg

remove_clock

remove_clock_transitionremove_clock_uncertaintyremove_input_delay

remove_output_delayremove_driving_cellremove_wire_load_model

SyntaxChecking

Unix%dcprocheckconstr_file.con

PhysicalConstraints–TopographicalMode

set_aspect_ratio

set_utilization

set_placement_area

set_rectilinear_outlineset_port_side

set_port_location

set_cell_location

create_placement_keepout

Misc.Reports

#GenerateAlibraryreportfile

read_dblibrary_file.db

list_libs

redirect–filereports/lib.rpt{report_lib}report_hierarchy[-noleaf]

#Arithmeticimpl