CycloneIVSchematicReviewWorksheet.docx

CycloneIVSchematicReviewWorksheet.docx

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CycloneIVSchematicReviewWorksheet

Cyclone®IVDeviceSchematicReviewWorksheet

ThisdocumentisintendedtohelpyoureviewyourschematicandcomparethepinusageagainsttheCycloneIVDeviceFamilyPinConnectionGuidelines（PDF）version1.4andotherreferencedliteratureforthisdevicefamily.ThetechnicalcontentisdividedintofocusareassuchasFPGApowersupplies,configuration,transceivers,FPGAI/O,andexternalmemoryinterfaces.

Withineachfocusarea,thereisatablethatcontainsthevoltageorpinnameforallofthededicatedanddualpurposepinsforthedevicefamily.Insomecases,thedevicedensityandpackagecombinationmaynotincludesomeofthepinsshowninthisworksheet,youshouldcrossreferencewiththepin-outfileforyourspecificdevice.Linkstothedevicepin-outfilesareprovidedatthetopofeachsection.

Beforeyoubeginusingthisworksheettoreviewyourschematicandcommittoboardlayout,Alterahighlyrecommends:

1）ReviewthelatestversionoftheCycloneIVDeviceErrataSheet（noerrataexistsatthetimethisdocumentwaspublished）andtheKnowledgeDatabaseforCycloneIVDeviceKnownIssuesandCycloneIVDeviceHandbookKnownIssues.

2）CompileyourdesignintheQuartus®IIsoftwaretocompletion.

Forexample,therearemanyI/OrelatedplacementrestrictionsandVCCIOrequirementsfortheI/Ostandardsusedinthedevice.Ifyoudonothaveacompleteproject,thenataminimumatoplevelprojectshouldbeusedwithallI/Opinsdefined,placed,andapplyalloftheconfigurableoptionsthatyouplantouse.AllI/Orelatedmegafunctionsshouldalsobeincludedintheminimalproject,including,butnotlimitedto,externalmemoryinterfaces,PLLs,altlvds,altgx,andaltddio.TheI/OAnalysistoolinthePinPlannercanthenbeusedontheminimalprojecttovalidatethepinoutintheQuartusIIsoftwaretoassuretherearenoconflictswiththedevicerulesandguidelines.

WhenusingtheI/OAnalysistoolyoumustensuretherearenoerrorswithyourpinout.Additionally,youshouldcheckallwarningandcriticalwarningmessagestoevaluatetheirimpactonyourdesign.Youcanrightclickyourmouseoveranywarningorcriticalwarningmessageandselect“Help”.ThiswillbringopenanewHelpwindowwithfurtherinformationonthecauseofthewarning,andtheactionthatisrequired.

Forexample,thefollowingwarningisgeneratedwhenaPLLisdrivenbyaglobalnetworkwherethesourceisavaliddedicatedclockinputpin,butthepinisnotonededicatedtotheparticularPLL:

Warning:

PLL""inputclockinclk[0]isnotfullycompensatedandmayhavereducedjitterperformancebecauseitisfedbyanon-dedicatedinput

Info:

InputportINCLK[0]ofnode""isdrivenbyclock~clkctrlwhichisOUTCLKoutputportofClockControlBlocktypenodeclock~clkctrl

Thehelpfileprovidesthefollowing:

CAUSE:

ThespecifiedPLL'sinputclockisnotdrivenbyadedicatedinputpin.Asaresult,theinputclockdelaywillnotbefullycompensatedbythePLL.Additionally,jitterperformancedependsontheswitchingrateofotherdesignelements.Thiscanalsooccurifaglobalsignalassignmentisappliedtotheclockinputpin,whichforcestheclocktousethenon-dedicatedglobalclocknetwork.

ACTION:

Ifyouwantcompensationofthespecifiedinputclockorbetterjitterperformance,connecttheinputclockonlytoaninputpin,orassigntheinputpinonlytoadedicatedinputclocklocationforthePLL.Ifyoudonotwantcompensationofthespecifiedinputclock,thensetthePLLtoNoCompensationmode.

Whenassigningtheinputpintotheproperdedicatedclockpinlocation,refertoClockNetworksandPLLsinCycloneIVDevices（PDF）fortheproperportmappingofdedicatedclockinputpinstoPLLs.

TherearemanyreportsavailableforuseafterasuccessfulcompilationorI/Oanalysis.Forexample,youcanusethe“AllPackagePins”and“I/OBankUsage”reportswithintheCompilation–Fitter–ResourceSectiontoseealloftheI/OstandardsandI/Oconfigurableoptionsthatareassignedtoallofthepinsinyourdesign,aswellasviewtherequiredVCCIOforeachI/Obank.Thesereportsmustmatchyourschematicpinconnections.

Thereviewtablehasthefollowingheading:

Plane/Signal

SchematicName

ConnectionGuidelines

Comments/Issues

Thefirstcolumn（Plane/Signal）liststheFPGAvoltageorsignalpinname.Youshouldonlyeditthiscolumntoremovededicatedordualpurposepinnamesthatarenotavailableforyourdevicedensityandpackageoption.

Thesecondcolumn（SchematicName）isforyoutoenteryourschematicname（s）forthesignal（s）orplaneconnectedtotheFPGApin（s）.

Thethirdcolumn（ConnectionGuidelines）shouldbeconsidered“readonly”asthiscontainsAltera’srecommendedconnectionguidelinesforthevoltageplaneorsignal.

Thefourthcolumn（Comments/Issues）isanareaprovidedasa“notepad”foryoutocommentonanydeviationsfromtheconnectionguidelines,andtoverifyguidelinesaremet.Inmanycasestherearenotesthatprovidefurtherinformationanddetailthatcomplimenttheconnectionguidelines.

Hereisanexampleofhowtheworksheetcanbeused:

Plane/Signal

SchematicName

ConnectionGuidelines

Comments/Issues

VCCINT

+1.2V

Connectedto+1.2Vplane,noisolationisnecessary.

Missinglowandmediumrangedecoupling,checkPDN.

SeeNotes（1-1）（1-2）（1-3）（1-6）（1-7）.

LegalNote:

PLEASEREVIEWTHEFOLLOWINGTERMSANDCONDITIONSCAREFULLYBEFOREUSINGTHISSCHEMATICREVIEWWORKSHEET（“WORKSHEET”）PROVIDEDTOYOU.BYUSINGTHISWORKSHEET,YOUINDICATEYOURACCEPTANCEOFSUCHTERMSANDCONDITIONS,WHICHCONSTITUTETHELICENSEAGREEMENT（"AGREEMENT"）BETWEENYOUANDALTERACORPORATIONORITSAPPLICABLESUBSIDIARIES（"ALTERA"）.

1.SubjecttothetermsandconditionsofthisAgreement,Alteragrantstoyou,fornoadditionalfee,anon-exclusiveandnon-transferablerighttousethisWorksheetforthesolepurposeofverifyingthevalidityofthepinconnectionsofanAlteraprogrammablelogicdevice-baseddesign.YoumaynotusethisWorksheetforanyotherpurpose.TherearenoimpliedlicensesgrantedunderthisAgreement,andallrights,exceptforthosegrantedunderthisAgreement,remainwithAltera.

2.Alteradoesnotguaranteeorimplythereliability,orserviceability,ofthisWorksheetorotheritemsprovidedaspartofthisWorksheet.ThisWorksheetisprovided'ASIS'.ALTERADISCLAIMSALLWARRANTIES,EXPRESSORIMPLIED,INCLUDINGTHEIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ANDNON-INFRINGEMENT.ALTERAHASNOOBLIGATIONTOPROVIDEYOUWITHANYSUPPORTORMAINTENANCE.

3.InnoeventshalltheaggregateliabilityofAlterarelatingtothisAgreementorthesubjectmatterhereofunderanylegaltheory（whetherintort,contract,orotherwise）,exceedOneHundredUS Dollars（US$100.00）.InnoeventshallAlterabeliableforanylostrevenue,lostprofits,orotherconsequential,indirect,orspecialdamagescausedbyyouruseofthisWorksheetevenifadvisedofthepossibilityofsuchdamages.

4.ThisAgreementmaybeterminatedbyeitherpartyforanyreasonatanytimeupon30-days’priorwrittennotice.ThisAgreementshallbegovernedbythelawsoftheStateofCalifornia,withoutregardtoconflictoflaworchoiceoflawprinciples.YouagreetosubmittotheexclusivejurisdictionofthecourtsintheCountyofSantaClara,StateofCaliforniafortheresolutionofanydisputeorclaimarisingoutoforrelatingtothisAgreement.Thepartiesherebyagreethatthepartywhoisnotthesubstantiallyprevailingpartywithrespecttoadispute,claim,orcontroversyrelatingtothisAgreementshallpaythecostsactuallyincurredbythesubstantiallyprevailingpartyinrelationtosuchdispute,claim,orcontroversy,includingattorneys'fees.FailuretoenforceanytermorconditionofthisAgreementshallnotbedeemedawaiveroftherighttolaterenforcesuchtermorconditionoranyothertermorconditionoftheAgreement.

BYUSINGTHISWORKSHEET,YOUACKNOWLEDGETHATYOUHAVEREADTHISAGREEMENT,UNDERSTANDIT,ANDAGREETOBEBOUNDBYITSTERMSANDCONDITIONS.YOUANDALTERAFURTHERAGREETHATITISTHECOMPLETEANDEXCLUSIVESTATEMENTOFTHEAGREEMENTBETWEENYOUANDALTERA,WHICHSUPERSEDESANYPROPOSALORPRIORAGREEMENT,ORALORWRITTEN,ANDANYOTHERCOMMUNICATIONSBETWEENYOUANDALTERARELATINGTOTHESUBJECTMATTEROFTHISAGREEMENT.

Index

SectionI:

Power

SectionII:

Configuration

SectionIII:

Transceiver

SectionIV:

I/O

a:

ClockPins

b:

DedicatedandDualPurposePins

c:

DualPurposeDifferentialI/Opins

SectionV:

ExternalMemoryInterfacePins

a:

DDR/2InterfacePins

b:

DDR/2TerminationGuidelines

SectionVI:

DocumentRevisionHistory

SectionI:

Power

CycloneIVRecommendedReferenceLiterature/ToolList

CycloneIVPinOutFiles

CycloneIVDeviceFamilyPinConnectionGuidelines（PDF）

CycloneIIIandCycloneIVPowerPlayEarlyPowerEstimator

CycloneIIIandCycloneIVPowerPlayEarlyPowerEstimatorUserGuide（PDF）

PowerDeliveryNetwork（PDN）ToolForArria®V,Stratix®V,CycloneIV,andArriaIIGZDevices

Device-SpecificPowerDeliveryNetwork（PDN）ToolUserGuide（PDF）

PowerPlayPowerAnalyzerSupportResources

AN592:

CycloneIVDesignGuidelines（PDF）

AN583:

DesigningPowerIsolationFilterswithFerriteBeadsforAlteraFPGAs（PDF）

AN597:

GettingStartedFlowforBoardDesigns（PDF）

AlteraBoardDesignResourceCenter（Generalboarddesignguidelines,PDNdes