CycloneIVSchematicReviewWorksheet.docx

1、CycloneIVSchematicReviewWorksheetCyclone IV Device Schematic Review WorksheetThis document is intended to help you review your schematic and compare the pin usage against the Cyclone IV Device Family Pin Connection Guidelines (PDF) version 1.4 and other referenced literature for this device family.

2、The technical content is divided into focus areas such as FPGA power supplies, configuration, transceivers, FPGA I/O, and external memory interfaces. Within each focus area, there is a table that contains the voltage or pin name for all of the dedicated and dual purpose pins for the device family. I

3、n some cases, the device density and package combination may not include some of the pins shown in this worksheet, you should cross reference with the pin-out file for your specific device. Links to the device pin-out files are provided at the top of each section.Before you begin using this workshee

4、t to review your schematic and commit to board layout, Altera highly recommends:1) Review the latest version of the Cyclone IV Device Errata Sheet (no errata exists at the time this document was published) and the Knowledge Database for Cyclone IV Device Known Issues and Cyclone IV Device Handbook K

5、nown Issues. 2) Compile your design in the Quartus II software to completion. For example, there are many I/O related placement restrictions and VCCIO requirements for the I/O standards used in the device. If you do not have a complete project, then at a minimum a top level project should be used wi

6、th all I/O pins defined, placed, and apply all of the configurable options that you plan to use. All I/O related megafunctions should also be included in the minimal project, including, but not limited to, external memory interfaces, PLLs, altlvds, altgx, and altddio. The I/O Analysis tool in the Pi

7、n Planner can then be used on the minimal project to validate the pinout in the Quartus II software to assure there are no conflicts with the device rules and guidelines.When using the I/O Analysis tool you must ensure there are no errors with your pinout. Additionally, you should check all warning

8、and critical warning messages to evaluate their impact on your design. You can right click your mouse over any warning or critical warning message and select “Help”. This will bring open a new Help window with further information on the cause of the warning, and the action that is required.For examp

9、le, the following warning is generated when a PLL is driven by a global network where the source is a valid dedicated clock input pin, but the pin is not one dedicated to the particular PLL:Warning: PLL input clock inclk0 is not fully compensated and may have reduced jitter performance because it is

10、 fed by a non-dedicated input Info: Input port INCLK0 of node is driven by clockclkctrl which is OUTCLK output port of Clock Control Block type node clockclkctrlThe help file provides the following:CAUSE:The specified PLLs input clock is not driven by a dedicated input pin. As a result, the input cl

11、ock delay will not be fully compensated by the PLL. Additionally, jitter performance depends on the switching rate of other design elements. This can also occur if a global signal assignment is applied to the clock input pin, which forces the clock to use the non-dedicated global clock network.ACTIO

12、N:If you want compensation of the specified input clock or better jitter performance, connect the input clock only to an input pin, or assign the input pin only to a dedicated input clock location for the PLL. If you do not want compensation of the specified input clock, then set the PLL to No Compe

13、nsation mode.When assigning the input pin to the proper dedicated clock pin location, refer to Clock Networks and PLLs in Cyclone IV Devices (PDF) for the proper port mapping of dedicated clock input pins to PLLs.There are many reports available for use after a successful compilation or I/O analysis

14、. For example, you can use the “All Package Pins” and “I/O Bank Usage” reports within the Compilation Fitter Resource Section to see all of the I/O standards and I/O configurable options that are assigned to all of the pins in your design, as well as view the required VCCIO for each I/O bank. These

15、reports must match your schematic pin connections.The review table has the following heading:Plane/SignalSchematic NameConnection GuidelinesComments / IssuesThe first column (Plane/Signal) lists the FPGA voltage or signal pin name. You should only edit this column to remove dedicated or dual purpose

16、 pin names that are not available for your device density and package option.The second column (Schematic Name) is for you to enter your schematic name(s) for the signal(s) or plane connected to the FPGA pin(s).The third column (Connection Guidelines) should be considered “read only” as this contain

17、s Alteras recommended connection guidelines for the voltage plane or signal. The fourth column (Comments/Issues) is an area provided as a “notepad” for you to comment on any deviations from the connection guidelines, and to verify guidelines are met. In many cases there are notes that provide furthe

18、r information and detail that compliment the connection guidelines.Here is an example of how the worksheet can be used:Plane/SignalSchematic NameConnection GuidelinesComments / IssuesVCCINT+1.2VConnected to +1.2V plane, no isolation is necessary. Missing low and medium range decoupling, check PDN.Se

19、e Notes (1-1) (1-2) (1-3) (1-6) (1-7).Legal Note: PLEASE REVIEW THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE USING THIS SCHEMATIC REVIEW WORKSHEET (“WORKSHEET”) PROVIDED TO YOU. BY USING THIS WORKSHEET, YOU INDICATE YOUR ACCEPTANCE OF SUCH TERMS AND CONDITIONS, WHICH CONSTITUTE THE LICENSE AG

20、REEMENT (AGREEMENT) BETWEEN YOU AND ALTERA CORPORATION OR ITS APPLICABLE SUBSIDIARIES (ALTERA).1. Subject to the terms and conditions of this Agreement, Altera grants to you, for no additional fee, a non-exclusive and non-transferable right to use this Worksheet for the sole purpose of verifying the

21、 validity of the pin connections of an Altera programmable logic device-based design. You may not use this Worksheet for any other purpose. There are no implied licenses granted under this Agreement, and all rights, except for those granted under this Agreement, remain with Altera.2. Altera does not

22、 guarantee or imply the reliability, or serviceability, of this Worksheet or other items provided as part of this Worksheet. This Worksheet is provided AS IS. ALTERA DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, A

23、ND NON-INFRINGEMENT. ALTERA HAS NO OBLIGATION TO PROVIDE YOU WITH ANY SUPPORT OR MAINTENANCE.3. In no event shall the aggregate liability of Altera relating to this Agreement or the subject matter hereof under any legal theory (whether in tort, contract, or otherwise), exceed One Hundred USDollars (

24、US$100.00). In no event shall Altera be liable for any lost revenue, lost profits, or other consequential, indirect, or special damages caused by your use of this Worksheet even if advised of the possibility of such damages.4. This Agreement may be terminated by either party for any reason at any ti

25、me upon 30-days prior written notice. This Agreement shall be governed by the laws of the State of California, without regard to conflict of law or choice of law principles. You agree to submit to the exclusive jurisdiction of the courts in the County of Santa Clara, State of California for the reso

26、lution of any dispute or claim arising out of or relating to this Agreement. The parties hereby agree that the party who is not the substantially prevailing party with respect to a dispute, claim, or controversy relating to this Agreement shall pay the costs actually incurred by the substantially pr

27、evailing party in relation to such dispute, claim, or controversy, including attorneys fees. Failure to enforce any term or condition of this Agreement shall not be deemed a waiver of the right to later enforce such term or condition or any other term or condition of the Agreement. BY USING THIS WOR

28、KSHEET, YOU ACKNOWLEDGE THAT YOU HAVE READ THIS AGREEMENT, UNDERSTAND IT, AND AGREE TO BE BOUND BY ITS TERMS AND CONDITIONS. YOU AND ALTERA FURTHER AGREE THAT IT IS THE COMPLETE AND EXCLUSIVE STATEMENT OF THE AGREEMENT BETWEEN YOU AND ALTERA, WHICH SUPERSEDES ANY PROPOSAL OR PRIOR AGREEMENT, ORAL OR

29、 WRITTEN, AND ANY OTHER COMMUNICATIONS BETWEEN YOU AND ALTERA RELATING TO THE SUBJECT MATTER OF THIS AGREEMENT.IndexSection I: Power Section II: ConfigurationSection III: TransceiverSection IV: I/O a: Clock Pins b: Dedicated and Dual Purpose Pins c: Dual Purpose Differential I/O pinsSection V: Exter

30、nal Memory Interface Pins a: DDR/2 Interface Pins b: DDR/2 Termination GuidelinesSection VI: Document Revision HistorySection I: Power Cyclone IV Recommended Reference Literature/Tool ListCyclone IV Pin Out Files Cyclone IV Device Family Pin Connection Guidelines (PDF)Cyclone III and Cyclone IV Powe

31、rPlay Early Power EstimatorCyclone III and Cyclone IV PowerPlay Early Power Estimator User Guide (PDF) Power Delivery Network (PDN) Tool For Arria V, Stratix V, Cyclone IV, and Arria II GZ DevicesDevice-Specific Power Delivery Network (PDN) Tool User Guide (PDF)PowerPlay Power Analyzer Support ResourcesAN 592: Cyclone IV Design Guidelines (PDF)AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs (PDF)AN 597: Getting Started Flow for Board Designs (PDF)Altera Board Design Resource Center (General board design guidelines, PDN des