tsmc025和035um设计规则.docx
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tsmc025和035um设计规则
2设计规则
设计规则几何关系定义
Width：
Sapcing:
Extension：
一几何图形内边界到另一图形外边界长度
Overlap：
一几何图形内边界到另一图形内边界长度
2.2设计规则
[4M2]lambda＝
[5M]lambda＝
2.2.1Well[
Description
SUBM
DEEP
Minimumwidth
12
12
Minimumspacingbetweenwellsatdifferentpotential
18
18
Minimumspacingbetweenwellsatsamepotential
6
6
Minimumspacingbetweenwellsofdifferenttype
0
0
2.2.2Active[
Description
SUBM
DEEP
Minimumwidth
3
3
Minimumspacing
3
3
Source/drainactivetowelledge
6
6
Substrate/wellcontactactivetowelledge
3
3
Minimumspacingbetweenactiveofdifferentimplant
4
4
2.2.3ThickActive[isalayerusedforthoseprocessesofferingtwodifferentthicknessesofgateoxide（typicallyforthelayoutoftransistorsthatoperateattwodifferentvoltagelevels）.TheACTIVElayerisusedtodelineatealltheactiveareas,regardlessofgateoxidethickness.THICK_ACTIVEisusedtotomarkthoseACTIVEareasthatwillhavethethickergateoxide;ACTIVEareasoutsideTHICK_ACTIVEwillhavethethinnergateoxide.
Rule
Description
SUBM
DEEP
Minimumwidth
4
4
Minimumspacing
4
4
MinimumACTIVEoverlap
4
4
MinimumspacetoexternalACTIVE
4
4
MinimumpolywidthinaTHICK_ACTIVEgate
3
3
2.2.4Poly[
Description
SUBM
DEEP
Minimumwidth
2
2
Minimumspacingoverfield
3
3
Minimumspacingoveractive
3
4
Minimumgateextensionofactive
2
Minimumactiveextensionofpoly
3
4
Minimumfieldpolytoactive
1
1
2.2.5SilicideBlock[
SBwidth
4
MinimumSBspacing
4
Minimumspacing,SBtocontact（nocontactsallowedinsideSB）
2
Minimumspacing,SBtoexternalactive
2
Minimumspacing,SBtoexternalpoly
2
ResistorispolyinsideSB;polyendsstickoutforcontacts
theentireresistormustbeoutsidewellandoverfield
N/A
Minimumpolywidthinresistor
5
Minimumspacingofpolyresistors（inasingleSBregion）
7
MinimumSBoverlapofpoly
2
2.2.6Select[
Description
SUBM
DEEP
Minimumselectspacingtochanneloftransistor
3
3
Minimumselectoverlapofactive
2
2
Minimumselectoverlapofcontact
1
Minimumselectwidthandspacing（Note:
P-selectandN-selectmaybecoincident,butmustnotoverlap）
2
4
2.2.7ElectrodeforCapacitor[poly2layerisasecondpolysiliconlayer（physicallyabovethestandard,orfirst,polylayer）.Theoxidebetweenthetwopolysisthecapacitordielectric.Thecapacitorareaistheareaofcoincidentpolyandelectrode.
Rule
Description
SUBM
DEEP
Minimumwidth
7
n/a
Minimumspacing
3
Minimumpolyoverlap
5
Minimumspacingtoactiveorwelledge（notillustrated）
2
Minimumspacingtopolycontact
6
Minimumspacingtounrelatedmetal
2
2.2.8ElectrodeContact[poly2iscontactedthroughthestandardcontactlayer,similartothefirstpoly.Theoverlapnumbersarelarger,however.
Rule
Description
SUBM
DEEP
Exactcontactsize
2x2
n/a
Minimumcontactspacing
3
Minimumelectrodeoverlap（oncapacitor）
3
Minimumelectrodeoverlap（notoncapacitor）
2
Minimumspacingtopolyoractive
3
2.2.9ContacttoPoly[
Description
SUBM
DEEP
Exactcontactsize
2x2
2x2
Minimumpolyoverlap
Minimumcontactspacing
3
4
Minimumspacingtogateoftransistor
2
2
2.2.10ContacttoActive[
Description
SUBM
DEEP
Exactcontactsize
2x2
2x2
Minimumactiveoverlap
Minimumcontactspacing
3
4
Minimumspacingtogateoftransistor
2
2
2.2.11Metal1[
Description
SUBM
DEEP
Minimumwidth
3
3
Minimumspacing
3
3
Minimumoverlapofanycontact
1
1
Minimumspacingwhenmetallineiswiderthan10lambda
6
6
2.2.12Via[
Description
SUBM
DEEP
Exactsize
2x2
3x3
Minimumvia1spacing
3
3
Minimumoverlapbymetal1
1
1
Minimumspacingtocontact
2
n/a
Minimumspacingtopolyoractiveedge
2
n/a
2.2.13Metal2[
Description
SUBM
DEEP
Minimumwidth
3
3
Minimumspacing
3
4
Minimumoverlapofvia1
1
1
Minimumspacingwhenmetallinewiderthan10lambda
6
8
2.2.14Via2[
Description
SUBM
DEEP
Exactsize
2x2
3x3
Minimumspacing
3
3
Minimumoverlapbymetal2
1
n/a
Minimumspacingtovia1
2
n/a
2.2.14Metal3[
Description
SUBM
DEEP
Minimumwidth
3
3
Minimumspacingtometal3
3
4
Minimumoverlapofvia2
1
1
Minimumspacingwhenmetallineiswiderthan10lambda
6
8
2.2.15Via3[
Rule
Description
SUBM
DEEP
Exactsize
2x2
3x3
Minimumspacing
3
3
MinimumoverlapbyMetal3
1
1
2.2.16Metal4[
Rule
Description
SUBM
DEEP
METAL4width
6
3
METAL4space
6
4
METAL4overlapofVIA3
2
1
Minimumspacingwhenmetallineiswiderthan10lambda
12
8
2.2.17CAP_TOP_METAL[CAP_TOP_METALlayerisusedexclusivelyfortheconstructionofmetal-to-metalcapacitors.Thebottomplateofthecapacitorisoneoftheregularmetallayers,asspecifiedbelow.CAP_TOP_METAListheupperplateofthecapacitor;itissandwichedphysicallybetweenthebottomplatemetalandthenextmetallayerabove,withathindielectricbetweenthebottomandtopplates.
TheCAP_TOP_METALcanonlybecontactedfromthemetalabove;thebottomplatemetalcanbecontactedfrombeloworabove（subject,ineithercase,torule.CAP_TOP_METALmustalwaysbecontainedentirelywithinthebottomplatemetal.
Process
BottomPlate
TopPlate
TopPlateContact
TSMC_025
METAL4
CAP_TOP_METAL
VIA4andMETAL5
Rule
Description
Lambda
MinimumWidth,Capacitor
50
MinimumSpacing（2capacitorssharingasinglebottomplate）
2
Minimumbottommetaloverlap
5
Minimumoverlapofvia
3
Minimumspacingtobottommetalvia
5
Minimumbottommetaloverlapofitsvia
5
2.2.18Via4（DEEP）[
Rule
Description
Lambda
Exactsize
3x3
Minimumspacing
3
MinimumoverlapbyMetal4
1
2.2.19Metal5（DEEP）[
Rule
Description
5MetalProcess
Minimumwidth
4
MinimumspacingtoMetal5
4
MinimumoverlapofVia4
2
2.2.20Overglass[thatrulesinthissectionareinunitsofmicrons.Theyarenot"true"designrules,buttheydomakegoodpracticerules.Unfortunately,therearenoreallygoodgenericpaddesignrulessincepadsareprocess-specific.
Rule
Description
Microns
Minimumbondingpassivationopening
60
Minimumprobepassivationopening
20
Padmetaloverlapofpassivation
6
Minimumpadspacingtounrelatedmetal
30
Minimumpadspacingtoactive,polyorpoly2
15
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