s5pv210 uboot10移植三 之支持SPL.docx
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s5pv210uboot10移植三之支持SPL
s5pv210uboot-2012-10移植（三）之支持SPL
上次的uboot的BL1是自己实现的，今天就来让uboot-2012-10支持SPL功能，但不是完全用的uboot本身的代码，也不知道这样是好还是坏。
1.分析顶层目录的Makefile可以知道，需要添加CONFIG_SPL配置，这在前面的已经说过了，跟踪start.S代码，得知编译需要arch/arm/lib/spl.c文件，查看arch/arm/lib/Makefile得知，需要添加CONFIG_SPL_FRAMEWORK配置，所以include/configs/smdkv210.h+70添加[cpp]viewplaincopy?
/*SPL*/
#defineCONFIG_SPL
#defineCONFIG_SPL_FRAMEWORK2.因为SPL不需要BSS清零，所以修改arch/arm/cpu/armv7/start.S+128[cpp]viewplaincopy?
#ifndefCONFIG_SPL_BUILD
//byZheGaoclearbss
ldrr0,=__bss_start
ldrr1,=__bss_end__
movr2,#0x0
1:
strr2,[r0],#4
cmpr0,r1
bne1b
//endofclearbss
blsave_boot_params
#endif
3.因为BL1需要初始化memory，所以在lowlevel_init中添加，board/samsung/smdkv210/lowlevel_init.S+43[cpp]viewplaincopy?
#ifdefCONFIG_SPL_BUILD
blmem_ctrl_asm_init
#endif
4.mem_ctrl_asm_init在同目录下的mem_setup.S文件中，修改board/samsung/smdkv210/mem_setup.S添加memory的配置[cpp]viewplaincopy?
#defineELFIN_GPIO_BASE0xE0200000
#defineMP1_0DRV_SR_OFFSET0x3CC
#defineMP1_1DRV_SR_OFFSET0x3EC
#defineMP1_2DRV_SR_OFFSET0x40C
#defineMP1_3DRV_SR_OFFSET0x42C
#defineMP1_4DRV_SR_OFFSET0x44C
#defineMP1_5DRV_SR_OFFSET0x46C
#defineMP1_6DRV_SR_OFFSET0x48C
#defineMP1_7DRV_SR_OFFSET0x4AC
#defineMP1_8DRV_SR_OFFSET0x4CC
#defineMP2_0DRV_SR_OFFSET0x4EC
#defineMP2_1DRV_SR_OFFSET0x50C
#defineMP2_2DRV_SR_OFFSET0x52C
#defineMP2_3DRV_SR_OFFSET0x54C
#defineMP2_4DRV_SR_OFFSET0x56C
#defineMP2_5DRV_SR_OFFSET0x58C
#defineMP2_6DRV_SR_OFFSET0x5AC
#defineMP2_7DRV_SR_OFFSET0x5CC
#defineMP2_8DRV_SR_OFFSET0x5EC
#defineAPB_DMC_0_BASE0xF0000000
#defineAPB_DMC_1_BASE0xF1400000
#defineASYNC_MSYS_DMC0_BASE0xF1E00000
#defineDMC_CONCONTROL0x00
#defineDMC_MEMCONTROL0x04
#defineDMC_MEMCONFIG00x08
#defineDMC_MEMCONFIG10x0C
#defineDMC_DIRECTCMD0x10
#defineDMC_PRECHCONFIG0x14
#defineDMC_PHYCONTROL00x18
#defineDMC_PHYCONTROL10x1C
#defineDMC_RESERVED0x20
#defineDMC_PWRDNCONFIG0x28
#defineDMC_TIMINGAREF0x30
#defineDMC_TIMINGROW0x34
#defineDMC_TIMINGDATA0x38
#defineDMC_TIMINGPOWER0x3C
#defineDMC_PHYSTATUS0x40
#defineDMC_CHIP0STATUS0x48
#defineDMC_CHIP1STATUS0x4C
#defineDMC_AREFSTATUS0x50
#defineDMC_MRSTATUS0x54
#defineDMC_PHYTEST00x58
#defineDMC_PHYTEST10x5C
#defineDMC_QOSCONTROL00x60
#defineDMC_QOSCONFIG00x64
#defineDMC_QOSCONTROL10x68
#defineDMC_QOSCONFIG10x6C
#defineDMC_QOSCONTROL20x70
#defineDMC_QOSCONFIG20x74
#defineDMC_QOSCONTROL30x78
#defineDMC_QOSCONFIG30x7C
#defineDMC_QOSCONTROL40x80
#defineDMC_QOSCONFIG40x84
#defineDMC_QOSCONTROL50x88
#defineDMC_QOSCONFIG50x8C
#defineDMC_QOSCONTROL60x90
#defineDMC_QOSCONFIG60x94
#defineDMC_QOSCONTROL70x98
#defineDMC_QOSCONFIG70x9C
#defineDMC_QOSCONTROL80xA0
#defineDMC_QOSCONFIG80xA4
#defineDMC_QOSCONTROL90xA8
#defineDMC_QOSCONFIG90xAC
#defineDMC_QOSCONTROL100xB0
#defineDMC_QOSCONFIG100xB4
#defineDMC_QOSCONTROL110xB8
#defineDMC_QOSCONFIG110xBC
#defineDMC_QOSCONTROL120xC0
#defineDMC_QOSCONFIG120xC4
#defineDMC_QOSCONTROL130xC8
#defineDMC_QOSCONFIG130xCC
#defineDMC_QOSCONTROL140xD0
#defineDMC_QOSCONFIG140xD4
#defineDMC_QOSCONTROL150xD8
#defineDMC_QOSCONFIG150xDC
#defineDMC0_MEMCONFIG_00x20E01323//MemConfig0256MBconfig,8banks,MappingMethod[12:
15]0:
linear,1:
linterleaved,2:
Mixed
#defineDMC0_MEMCONFIG_10x40F01323//MemConfig1
#defineDMC0_TIMINGA_REF0x00000618//TimingAref7.8us*133MHz=1038（0x40E）,100MHz=780（0x30C）,20MHz=156（0x9C）,10MHz=78（0x4E）
#defineDMC0_TIMING_ROW0x28233287//TimingRowfor@200MHz
#defineDMC0_TIMING_DATA0x23240304//TimingDataCL=3
#defineDMC0_TIMING_PWR0x09C80232//TimingPower
#defineDMC1_MEMCONTROL0x00202400//MemControlBL=4,2chip,DDR2type,dynamicselfrefresh,forceprecharge,dynamicpowerdownoff
#defineDMC1_MEMCONFIG_00x40C01323//MemConfig0512MBconfig,8banks,MappingMethod[12:
15]0:
linear,1:
linterleaved,2:
Mixed
#defineDMC1_MEMCONFIG_10x00E01323//MemConfig1
#defineDMC1_TIMINGA_REF0x00000618//TimingAref7.8us*133MHz=1038（0x40E）,100MHz=780（0x30C）,20MHz=156（0x9C）,10MHz=78（0x4
#defineDMC1_TIMING_ROW0x28233289//TimingRowfor@200MHz
#defineDMC1_TIMING_DATA0x23240304//TimingDataCL=3
#defineDMC1_TIMING_PWR0x08280232//TimingPower
.globlmem_ctrl_asm_init
mem_ctrl_asm_init:
#if0
ldrr6,=S5PC100_DMC_BASE@0xE6000000
/*DLLparametersetting*/
ldrr1,=0x50101000
strr1,[r6,#0x018]@PHYCONTROL0
ldrr1,=0xf4
strr1,[r6,#0x01C]@PHYCONTROL1
ldrr1,=0x0
strr1,[r6,#0x020]@PHYCONTROL2
/*DLLon*/
ldrr1,=0x50101002
strr1,[r6,#0x018]@PHYCONTROL0
/*DLLstart*/
ldrr1,=0x50101003
strr1,[r6,#0x018]@PHYCONTROL0
/*ForcevaluelockingforDLLoff*/
strr1,[r6,#0x018]@PHYCONTROL0
/*DLLoff*/
ldrr1,=0x50101001
strr1,[r6,#0x018]@PHYCONTROL0
/*autorefreshoff*/
ldrr1,=0xff001010
strr1,[r6,#0x000]@CONCONTROL
/*
*BurstLength4,2chips,32-bit,LPDDR
*OFF:
dynamicselfrefresh,forceprecharge,dynamicpowerdownoff
*/
ldrr1,=0x00212100
strr1,[r6,#0x004]@MEMCONTROL
/*
*Note:
*IfBank0hasOneDRAMweplaceitat0x2800'0000
*SofinallyBank1shouldaddressstartatat0x2000'0000
*/
movr4,#0x0
swap_memory:
/*
*Bank0
*0x30->0x30000000
*0xf8->0x37FFFFFF
*[15:
12]0:
Linear
*[11:
8]2:
9bits
*[7:
4]2:
14bits
*[3:
0]2:
4banks
*/
ldrr1,=0x30f80222
/*ifr4is1,swapthebank*/
cmpr4,#0x1
orreqr1,r1,#0x08000000
strr1,[r6,#0x008]@MEMCONFIG0
/*
*Bank1
*0x38->0x38000000
*0xf8->0x3fFFFFFF
*[15:
12]0:
Linear
*[11:
8]2:
9bits
*[7:
4]2:
14bits
*[3:
0]2:
4banks
*/
ldrr1,=0x38f80222
/*ifr4is1,swapthebank*/
cmpr4,#0x1
biceqr1,r1,#0x08000000
strr1,[r6,#0x00c]@MEMCONFIG1
ldrr1,=0x20000000
strr1,[r6,#0x014]@PRECHCONFIG
/*
*FIXME:
Pleaseverifythesevalues
*7.8us*166MHz%LE%LONG1294（0x50E）
*7.8us*133MHz%LE%LONG1038（0x40E）,
*7.8us*100MHz%LE%LONG780（0x30C）,
*7.8us*20MHz%LE%LONG156（0x9C）,
*7.8us*10MHz%LE%LONG78（0x4E）
*/
ldrr1,=0x0000050e
strr1,[r6,#0x030]@TIMINGAREF
/*166MHz*/
ldrr1,=0x0c233287
strr1,[r6,#0x034]@TIMINGROW
/*twtr=3twr=2trtp=3cl=3wl=3rl=3*/
ldrr1,=0x32330303
strr1,[r6,#0x038]@TIMINGDATA
/*tfaw=4sxsr=0x14txp=0x14tcke=3tmrd=3*/
ldrr1,=0x04141433
strr1,[r6,#0x03C]@TIMINGPOWER
/*chip0Deselect*/
ldrr1,=0x07000000
strr1,[r6,#0x010]@DIRECTCMD
/*chip0PALL*/
ldrr1,=0x01000000
strr1,[r6,#0x010]@DIRECTCMD
/*chip0REFA*/
ldrr1,=0x05000000
strr1,[r6,#0x010]@DIRECTCMD
/*chip0REFA*/
strr1,[r6,#0x010]@DIRECTCMD
/*chip0MRS,CL%LE%LONG3,BL%LE%LONG4*/
ldrr1,=0x00000032
strr1,[r6,#0x010]@DIRECTCMD
/*chip1Deselect*/
ldrr1,=0x07100000
strr1,[r6,#0x010]@DIRECTCMD
/*chip1PALL*/
ldrr1,=0x01100000
strr1,[r6,#0x010]@DIRECTCMD
/*chip1REFA*/
ldrr1,=0x05100000
strr1,[r6,#0x010]@DIRECTCMD
/*chip1REFA*/
strr1,[r6,#0x010]@DIRECTCMD
/*chip1MRS,CL%LE%LONG3,BL%LE%LONG4*/
ldrr1,=0x00100032
strr1,[r6,#0x010]@DIRECTCMD
/*autorefreshon*/
ldrr1,=0xff002030
strr1,[r6,#0x000]@CONCONTROL
/*PwrdnConfig*/
ldrr1,=0x00100002
strr1,[r6,#0x028]@PWRDNCONFIG
/*BL%LE%LONG*/
ldrr1,=0xff212100
strr1,[r6,#0x004]@MEMCONTROL
/*Trytotestmemoryarea*/
cmpr4,#0x1
beq1f
movr4,#0x1
ldrr1,=0x37ffff00
strr4,[r1]
strr4,[r1,#0x4]@dummywrite
ldrr0,[r1]
cmpr0,r4
bneswap_memory
#endif
/*DMC0DriveStrength（Setting2X）*/
ldrr0,=ELFIN_GPIO_BASE
ldrr1,=0x0000AAAA
strr1,[r0,#MP1_0DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP1_1DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP1_2DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP1_3DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP1_4DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP1_5DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP1_6DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP1_7DRV_SR_OFFSET]
ldrr1,=0x00002AAA
strr1,[r0,#MP1_8DRV_SR_OFFSET]
/*DMC1DriveStrength（Setting2X）*/
ldrr0,=ELFIN_GPIO_BASE
ldrr1,=0x0000AAAA
strr1,[r0,#MP2_0DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP2_1DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP2_2DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP2_3DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP2_4DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP2_5DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP2_6DRV_SR_OFFSET]
ldrr1,=0x0000AAAA
strr1,[r0,#MP2_7DRV_SR_OFFSET]
ldrr1,=0x00002AAA
strr1,[r0,#MP2_8DRV_SR_OFFSET]
/*DMC0initializationatsingleType*/
ldrr0,=APB_DMC_0_BASE
ldrr1,=0x00101000@PhyControl0DLLparametersetting,manual0x00101000
strr1,[r0,#DMC_PHYCONTROL0]
ldrr1,=0x00000086@PhyControl1DLLparametersetting,LPDDR/LPDDR2Case
strr1,[r0,#DMC_PHYCONTROL1]
ldrr1,=0x00101002@PhyControl0DLLon
strr1,[r0,#DMC_PHYCONTROL0]
ldrr1,=0x00101003@PhyControl0DLLstart
strr1,[r0,#DMC_PHYCONTROL0]
find_lock_val:
ldrr1,[r0,#DMC_PHYSTATUS]@LoadPhystatusregistervalu
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