EDA课程设计电子钟.docx
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EDA课程设计电子钟
EDA电子钟设计
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一，设计要求
设计一个电子时钟，要求可以显示时、分、秒，用户可以设置时间。
扩展功能要求：
跑表功能，闹钟功能，调整数码管的亮度。
二、VHDL代码
-------分频------
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpinis
port（
clk:
instd_logic;--10m频
clk_10000:
outstd_logic;--1000分频
clk_100:
outstd_logic;--100k分频
clk_1:
outstd_logic--10m分频
）;
endentity;
architectureoneoffenpinis
signalQ_1:
integerrange0to500;
signalQ_2:
integerrange0to50000;
signalQ_3:
integerrange0to5000000;
signalclk10000:
std_logic;
signalclk100:
std_logic;
signalclk1:
std_logic;
begin
fen1000:
process（clk）
begin
ifclk'eventandclk='1'then
ifQ_1=500then
Q_1<=0;
clk10000<=notclk10000;
elseQ_1<=Q_1+1;
endif;
endif;
endprocess;
fen100k:
process（clk）
begin
ifclk'eventandclk='1'then
ifQ_2=50000then
Q_2<=0;
clk100<=notclk100;
elseQ_2<=Q_2+1;
endif;
endif;
endprocess;
fen10m:
process（clk）
begin
ifclk'eventandclk='1'then
ifQ_3=5000000then
Q_3<=0;
clk1<=notclk1;
elseQ_3<=Q_3+1;
endif;
endif;
endprocess;
clk_10000<=clk10000;
clk_100<=clk100;
clk_1<=clk1;
endone;
------走表------
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityclockis
port（clk_1:
instd_logic;
key8:
instd_logic;
hs_set,hg_set,ms_set,mg_set,ss_set,sg_set:
inintegerrange0to9;
hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:
outintegerrange0to9）;
endentity;
architecturebhvofclockis
signalshi:
integerrange0to100;
signalfen:
integerrange0to100;
signalmiao:
integerrange0to100;
begin
process（clk_1,key8,hs_set,hg_set,ms_set,mg_set,ss_set,sg_set）
begin
ifkey8='1'then
shi<=hs_set*10+hg_set;
fen<=ms_set*10+mg_set;
miao<=ss_set*10+sg_set;
elsifclk_1'eventandclk_1='1'then
ifmiao=59then
miao<=0;
fen<=fen+1;
elsiffen>59then
fen<=0;
shi<=shi+1;
elsifshi>23then
shi<=0;
elsemiao<=miao+1;
endif;
endif;
endprocess;
sg_out<=miaorem10;
ss_out<=miao/10;
mg_out<=fenrem10;
ms_out<=fen/10;
hg_out<=shirem10;
hs_out<=shi/10;
end;
---设置时间---
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitysetis
port（module:
inintegerrange0to4;
key4,key1:
instd_logic;
hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:
outintegerrange0to9）;
endentity;
architecturebavofsetis
signala:
integerrange0to5;
signalshishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:
integerrange0to9;
begin
process（module,key4）
begin
ifmodule=1then
ifkey4'eventandkey4='1'then
ifa<5then
a<=a+1;
elsea<=0;
endif;
endif;
endif;
endprocess;
process（module,a,key1）
begin
ifmodule=1then
ifkey1'eventandkey1='1'then
caseais
when0=>
ifmiaoge1=9then
miaoge1<=0;
elsemiaoge1<=miaoge1+1;
endif;
when1=>
ifmiaoshi1=5then
miaoshi1<=0;
elsemiaoshi1<=miaoshi1+1;
endif;
when2=>
iffenge1=9then
fenge1<=0;
elsefenge1<=fenge1+1;
endif;
when3=>
iffenshi1=5then
fenshi1<=0;
elsefenshi1<=fenshi1+1;
endif;
when4=>
ifshige1=9then
shige1<=0;
elseshige1<=shige1+1;
endif;
when5=>
ifshishi1=2then
shishi1<=0;
elseshishi1<=shishi1+1;
endif;
endcase;
endif;
endif;
endprocess;
sg_out<=miaoge1;
ss_out<=miaoshi1;
mg_out<=fenge1;
ms_out<=fenshi1;
hg_out<=shige1;
hs_out<=shishi1;
end;
----模式转换----
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitychangeis
port（key7:
instd_logic;
module:
outintegerrange0to4）;
end;
architectureoneofchangeis
signalmo_s:
integerrange0to4;
begin
process（key7）
begin
ifkey7'eventandkey7='1'then
ifmo_s=4then
mo_s<=0;
elsemo_s<=mo_s+1;
endif;
endif;
endprocess;
module<=mo_s;
end;
--------五选一选择器--------
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityxuanzeis
port（module:
inintegerrange0to4;
shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:
inintegerrange0to9;
shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:
inintegerrange0to9;
shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3:
inintegerrange0to9;
fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:
inintegerrange0to9;
a0,a1,a3,a4,a6,a7:
outintegerrange0to9）;
endentityxuanze;
architecturebhvofxuanzeis
begin
process（shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1,
shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2,
shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3,
fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge,
module）
begin
casemoduleis
when0=>a0<=shishi1;a1<=shige1;a3<=fenshi1;a4<=fenge1;a6<=miaoshi1;a7<=miaoge1;
when1=>a0<=shishi2;a1<=shige2;a3<=fenshi2;a4<=fenge2;a6<=miaoshi2;a7<=miaoge2;
when2=>a0<=fenshi;a1<=fenge;a3<=miaoshi;a4<=miaoge;a6<=xmiaoshi;a7<=xmiaoge;
when3=>a0<=shishi3;a1<=shige3;a3<=fenshi3;a4<=fenge3;a6<=miaoshi3;a7<=miaoge3;
when4=>a0<=8;a1<=8;a3<=8;a4<=8;a6<=8;a7<=8;
endcase;
endprocess;
end;
-------秒表-------
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymiaobiaois
port（clk_100:
instd_logic;
module:
inintegerrange0to4;
key1,key4:
instd_logic;
ms_out,mg_out,ss_out,sg_out,sss_out,ssg_out:
outintegerrange0to9）;
endentity;
architecturebhvofmiaobiaois
signalfen,miao,xmiao:
integerrange0to99;
signalstart:
std_logic:
='0';
signalreset:
std_logic:
='0';
begin
process（clk_100,key1,key4,module,reset,start）
begin
ifmodule=2then
ifreset='1'then
fen<=0;
miao<=0;
xmiao<=0;
elsifstart='1'then
elsifclk_100'eventandclk_100='1'then
ifxmiao=99then
xmiao<=0;
miao<=miao+1;
elsifmiao>59then
miao<=0;
fen<=fen+1;
elsiffen>23then
fen<=0;
elsexmiao<=xmiao+1;
endif;
endif;
endif;
endprocess;
process（key4,start）
begin
ifkey4'eventandkey4='1'then
start<=notstart;
elsestart<=start;
endif;
endprocess;
process（key1,reset）
begin
ifkey1'eventandkey1='1'then
reset<=notreset;
elsereset<=reset;
endif;
endprocess;
ssg_out<=xmiaorem10;
sss_out<=xmiao/10;
sg_out<=miaorem10;
ss_out<=miao/10;
mg_out<=fenrem10;
ms_out<=fen/10;
end;
--------闹钟时间设置------
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityclocksetis
port（module:
inintegerrange0to4;
key4,key1:
instd_logic;
hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:
outintegerrange0to9）;
endentity;
architecturebavofclocksetis
signala:
integerrange0to5;
signalfenshi1,fenge1,miaoge1:
integerrange0to9;
signalshishi1:
integerrange0to9:
=1;
signalshige1:
integerrange0to9:
=2;
signalmiaoshi1:
integerrange0to9:
=0;
begin
process（module,key4）
begin
ifmodule=3then
ifkey4'eventandkey4='1'then
ifa<5then
a<=a+1;
elsea<=0;
endif;
endif;
endif;
endprocess;
process（module,a,key1）
begin
ifmodule=3then
ifkey1'eventandkey1='1'then
caseais
when0=>
ifmiaoge1=9then
miaoge1<=0;
elsemiaoge1<=miaoge1+1;
endif;
when1=>
ifmiaoshi1=5then
miaoshi1<=0;
elsemiaoshi1<=miaoshi1+1;
endif;
when2=>
iffenge1=9then
fenge1<=0;
elsefenge1<=fenge1+1;
endif;
when3=>
iffenshi1=5then
fenshi1<=0;
elsefenshi1<=fenshi1+1;
endif;
when4=>
ifshige1=9then
shige1<=0;
elseshige1<=shige1+1;
endif;
when5=>
ifshishi1=2then
shishi1<=0;
elseshishi1<=shishi1+1;
endif;
endcase;
endif;
endif;
endprocess;
sg_out<=miaoge1;
ss_out<=miaoshi1;
mg_out<=fenge1;
ms_out<=fenshi1;
hg_out<=shige1;
hs_out<=shishi1;
end;
------闹钟喇叭输出------
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityclocklabais
port（clk_100:
instd_logic;
hs1,hg1,ms1,mg1,ss1,sg1:
inintegerrange0to9;
hs2,hg2,ms2,mg2,ss2,sg2:
inintegerrange0to9;
laba:
outstd_logic）;
endentity;
architecturebavofclocklabais
begin
process（clk_100,
hs1,hg1,ms1,mg1,ss1,sg1,
hs2,hg2,ms2,mg2,ss2,sg2）
begin
ifhs2=hs1andhg2=hg1andms2=ms1and
mg2=mg1andss2=ss1andsg2=sg1then
laba<=clk_100;
elselaba<='1';
endif;
endprocess;
end;
---------扫描显示---------
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityscan_ledis
port（clk_10000:
instd_logic;
key4:
instd_logic;
module:
inintegerrange0to4;
a0,a1,a3,a4,a6,a7:
inintegerrange0to9;
sg:
outstd_logic_vector（6downto0）;
bt:
outstd_logic_vector（7downto0））;
end;
architectureoneofscan_ledis
signalcnt8:
std_logic_vector（2downto0）;--扫描计数信号
signala:
integerrange0to15;
signalliang:
std_logic;
signalflash:
integerrange0to2;
signalcount1,count2,count3:
integerrange0to10;
begin
p1:
process（cnt8,liang,a0,a1,a3,a4,a6,a7）
begin
casecnt8is
when"000"=>bt<="0000000"&（liang）;a<=a0;
when"001"=>bt<="000000"&（liang）&'0';a<=a1;
when"010"=>bt<="00000"&（liang）&"00";a<=15;
when"011"=>bt<="0000"&（liang）&"000";a<=a3;
when"100"=>bt<="000"&（liang）&"0000";a<=a4;
when"101"=>bt<="00"&（liang）&"00000";a<=15;
when"110"=>bt<='0'&（liang）&"000000";a<=a6;
when"111"=>bt<=（liang）&"0000000";a<=a7;
whenothers=>null;
endcase;
endprocessp1;
p2:
process（clk_10000）
begin
ifclk_10000'eventandclk_10000='1'thencnt8<=cnt8+1;
endif;
endprocessp2;
p3:
process（a）
begin
caseais--译码电路
when0=>sg<="0111111";
when1=>sg<="0000110";
when2=>sg<="1011011";
when3=>sg<="1001111";
when4=>sg<="1100110";
when5=>sg<="1101101";
when6=>sg<="1111101";
when7=>sg<="0000111";
when8=>sg<="1111111";
when9=>sg<="1101111";
wh
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