用VHDL语言实现拔河电路功能.docx
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用VHDL语言实现拔河电路功能
用VHDL语言实现拔河电路功能
实验四基于QuartusⅡ的硬件描述语言的拔河电路设计
1、实验内容
基于前期原理图电子拔河电路,甲、乙双方分别按动己方按键,按键的次数分别在双方的两个数码管上显示,当喊停止的时候,数码管数字较大的一方获胜,连续比赛多局以定胜负。
二、实验工具
1、DE0开发板一个
2、Quartus216软件
3、VHDL语言
三、实验准备
1、学习VHDL语言,了解基本语法规则和基本语句。
2、明确所实现的电路所需要的器件,并且明确用VHDL实现该器件的基本逻辑关系和基本语句。
实验所需要的器件为百进制计数器、比较器和译码器。
3、明确VHDL实体的定义,明确实体的输入输出,并且明确实现该实体的基本语法和基本步骤。
4、必须明确实体层次的概念,在低层次实体中,必须明确各个输入输出之间的联系,以结构的方式构建高层次实体。
四、实验程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYtest4IS
PORT(KEY1,KEY2,KEY3,CLOCK_IN:
INSTD_LOGIC;
HEX0,HEX1,HEX2,HEX3,HEX4,HEX5:
OUTSTD_LOGIC_VECTOR(6DOWNTO0);
com:
OUTSTD_LOGIC_VECTOR(2DOWNTO0));
ENDtest4;
--以下为百进制计数器设计实体--
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCOUNT_100IS
PORT(clk,clr:
INSTD_LOGIC;
--date_in:
INSTD_LOGIC_VECTOR(3DOWNTO0);
lo_out,hi_out:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOUNT_100;
ARCHITECTUREfwmOFCOUNT_100IS
SIGNALhi_tmp,lo_tmp:
STD_LOGIC_VECTOR(3DOWNTO0);
--SIGNALload_cnt:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
--load_cnt<=load&hi_lo;--数据写入与置数位控制的并置
PROCESS(clk,clr)
--hi_lo='1'时为高位置数,hi_lo='0'时为低位置数
--VARIABLEq_tmp:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
IFclr='0'THENhi_tmp<="0000";lo_tmp<="0000";--异步清零
ELSIFclk'EVENTANDclk='1'THEN
--IFload_cnt="10"THEN--低位置数
--IFdate_in>="1010"THENlo_tmp<="1001";
--ELSElo_tmp<=date_in;
--ENDIF;
--ELSIFload_cnt="11"THEN--高位置数
--IFdate_in>="1010"THENhi_tmp<="1001";
--ELSEhi_tmp<=date_in;
--ENDIF;
--ELSIFload_cnt="01"ORload_cnt="00"THEN
IFlo_tmp="1001"THEN--低位等于9
IFhi_tmp/="1001"THEN--如果高位不等于9
lo_tmp<="0000";hi_tmp<=hi_tmp+1;--那么高位加1
ELSE
hi_tmp<="0000";lo_tmp<="0000";
--ELSElo_tmp<="1001";--除此之外,低位9保持不变
ENDIF;
ELSElo_tmp<=lo_tmp+1;--如果低位不是9,那么低位加1
ENDIF;
--ENDIF;
ENDIF;
ENDPROCESS;
lo_out<=lo_tmp;--低位信号赋值给低位输出端
hi_out<=hi_tmp;--高位信号赋值给高位输出端
ENDfwm;
--以下为计算胜的局数的10进制计数器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCOUNT_10IS
PORT(clk,clr:
INSTD_LOGIC;
COUNT_10_OUT:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOUNT_10;
ARCHITECTUREfwmOFCOUNT_10IS
SIGNALCOUNT_10_TMP:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(clk,clr)
BEGINIFclr='0'THENCOUNT_10_TMP<="0000";--异步清零
ELSIFclk'EVENTANDclk='1'THEN
COUNT_10_TMP<=COUNT_10_TMP+1;
IFCOUNT_10_TMP="1001"THEN--如果加到十,归零
COUNT_10_TMP<="0000";
ENDIF;
ENDIF;
ENDPROCESS;
COUNT_10_OUT<=COUNT_10_TMP;
ENDfwm;
--以下为分频器实体电路
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYFPIS
PORT(clk_in:
INSTD_LOGIC;
clk_out:
OUTSTD_LOGIC);
ENDFP;
ARCHITECTUREfwmOFFPIS
CONSTANTM:
INTEGER:
=25000000;--50M分频到1HZ
SIGNALFP_TMP:
STD_LOGIC;
BEGIN
PROCESS(clk_in)
VARIABLECOUNT:
INTEGER:
=0;
BEGIN
IFclk_in'EVENTANDclk_in='1'THEN
COUNT:
=COUNT+1;--计数器+1
IFCOUNT<=MTHENFP_TMP<='0';
ELSIFCOUNTELSECOUNT:
=0;
ENDIF;
ENDIF;
ENDPROCESS;
clk_out<=FP_TMP;
ENDfwm;
--以下为七段数码管显示译码电路设计实体
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYDISIS
PORT(date_in:
INSTD_LOGIC_VECTOR(3DOWNTO0);
dis_out:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDDIS;
ARCHITECTUREfwmOFDISIS
BEGIN
PROCESS(date_in)
BEGIN
CASEdate_inIS
WHEN"0000"=>dis_out<="1000000";--显示0;
WHEN"0001"=>dis_out<="1111001";--显示1;
WHEN"0010"=>dis_out<="0100100";--显示2;
WHEN"0011"=>dis_out<="0110000";--显示3;
WHEN"0100"=>dis_out<="0011001";--显示4;
WHEN"0101"=>dis_out<="0010010";--显示5;
WHEN"0110"=>dis_out<="0000010";--显示6;
WHEN"0111"=>dis_out<="1111000";--显示7;
WHEN"1000"=>dis_out<="0000000";--显示8;
WHEN"1001"=>dis_out<="0010000";--显示9;
WHENOTHERS=>dis_out<="1111111";--不显示;
ENDCASE;
ENDPROCESS;
ENDfwm;
--以下为8位无符号整数比较器设计实体
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCOMPAREIS
PORT(a,b:
INSTD_LOGIC_VECTOR(7DOWNTO0);
eq,lt,gt:
OUTSTD_LOGIC);
ENDCOMPARE;
ARCHITECTUREfwmOFCOMPAREIS
BEGIN
PROCESS(a,b)
BEGIN
eq<='0';lt<='0';gt<='0';
IFa=bTHENeq<='1';
ENDIF;
IFaENDIF;
IFa>bTHENgt<='1';
ENDIF;
ENDPROCESS;
ENDfwm;
--以下为采用结构化描述test_6--
ARCHITECTUREfwmOFtest4IS
COMPONENTCOUNT_100
PORT(clk,clr:
INSTD_LOGIC;
--date_in:
INSTD_LOGIC_VECTOR(3DOWNTO0);
lo_out,hi_out:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENTCOUNT_100;
COMPONENTDIS
PORT(date_in:
INSTD_LOGIC_VECTOR(3DOWNTO0);
dis_out:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDCOMPONENTDIS;
COMPONENTCOMPARE
PORT(a,b:
INSTD_LOGIC_VECTOR(7DOWNTO0);
eq,lt,gt:
OUTSTD_LOGIC);
ENDCOMPONENTCOMPARE;
COMPONENTCOUNT_10
PORT(clk,clr:
INSTD_LOGIC;
COUNT_10_OUT:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENTCOUNT_10;
COMPONENTFP
PORT(clk_in:
INSTD_LOGIC;
clk_out:
OUTSTD_LOGIC);
ENDCOMPONENTFP;
SIGNALtem_lo_1,tem_hi_1,tem_lo_2,tem_hi_2:
STD_LOGIC_VECTOR(3DOWNTO0);
--定义百进制计数器输出中间变量
SIGNALCLK_OUT:
STD_LOGIC;--定义分频器输出中间信号
SIGNALCOUNT_10_DATE_OUT1,COUNT_10_DATE_OUT2:
STD_LOGIC_VECTOR(3DOWNTO0);--定义十进制计数器输出中间变量
SIGNALlt_mid,eq_mid,gt_mid:
STD_LOGIC;--定义比较器输出中间变量
---元件例化语句---
BEGIN
U0:
FPPORTMAP(clk_in=>CLOCK_IN,clk_out=>CLK_OUT);
U1:
COUNT_100PORTMAP(clk=>KEY1,CLR=>CLK_OUT,
lo_out=>tem_lo_1,
hi_out=>tem_hi_1);
U2:
COUNT_100PORTMAP(clk=>KEY2,CLR=>CLK_OUT,
lo_out=>tem_lo_2,
hi_out=>tem_hi_2);
U3:
DISPORTMAP(date_in=>tem_lo_1,
dis_out=>HEX0);
U4:
DISPORTMAP(date_in=>tem_hi_1,
dis_out=>HEX1);
U5:
DISPORTMAP(date_in=>tem_lo_2,
dis_out=>HEX2);
U6:
DISPORTMAP(date_in=>tem_hi_2,
dis_out=>HEX3);
U7:
COMPAREPORTMAP(a(0)=>tem_lo_1(0),a
(1)=>tem_lo_1
(1),a
(2)=>tem_lo_1
(2),a(3)=>tem_lo_1(3),
a(4)=>tem_hi_1(0),a(5)=>tem_hi_1
(1),a(6)=>tem_hi_1
(2),a(7)=>tem_hi_1(3),
b(0)=>tem_lo_2(0),b
(1)=>tem_lo_2
(1),b
(2)=>tem_lo_2
(2),b(3)=>tem_lo_2(3),
b(4)=>tem_hi_2(0),b(5)=>tem_hi_2
(1),b(6)=>tem_hi_2
(2),b(7)=>tem_hi_2(3),
lt=>lt_mid,eq=>eq_mid,gt=>gt_mid);
U8:
COMPAREPORTMAP(a(0)=>tem_lo_1(0),a
(1)=>tem_lo_1
(1),a
(2)=>tem_lo_1
(2),a(3)=>tem_lo_1(3),
a(4)=>tem_hi_1(0),a(5)=>tem_hi_1
(1),a(6)=>tem_hi_1
(2),a(7)=>tem_hi_1(3),
b(0)=>tem_lo_2(0),b
(1)=>tem_lo_2
(1),b
(2)=>tem_lo_2
(2),b(3)=>tem_lo_2(3),
b(4)=>tem_hi_2(0),b(5)=>tem_hi_2
(1),b(6)=>tem_hi_2
(2),b(7)=>tem_hi_2(3),
lt=>COM(0),eq=>COM
(1),gt=>COM
(2));
U9:
COUNT_10PORTMAP(clk=>lt_mid,clr=>KEY3,
COUNT_10_OUT=>COUNT_10_DATE_OUT1);
U10:
COUNT_10PORTMAP(clk=>gt_mid,clr=>KEY3,
COUNT_10_OUT=>COUNT_10_DATE_OUT2);
U11:
DISPORTMAP(date_in=>COUNT_10_DATE_OUT1,
dis_out=>HEX4);
U12:
DISPORTMAP(date_in=>COUNT_10_DATE_OUT2,
dis_out=>HEX5);
ENDfwm;
五、实验结果
1、没加五秒的脉冲之前的结果:
2、加了五秒脉冲后的结果