多路信号复用的基带发信系统.docx
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多路信号复用的基带发信系统
1.分频器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycount16is
port（clk:
instd_logic;
D,C,B,A:
outstd_logic）;
endcount16;
architecturertlofcount16is
signalcount_4:
std_logic_vector（3downto0）;
begin
process（clk）
begin
if（clk'eventandclk='1'）then
if（count_4="1111"）then
count_4<="0000";
else
count_4<=count_4+1;
endif;
endif;
endprocess;
2.内码产生器
libraryieee;
useieee.std_logic_1164.all;
entityneimacs0is
port（in0_8,in0_7,in0_6,in0_5,in0_4,in0_3,in0_2,in0_1,K3,K2,K1,sx0:
instd_logic;
out0:
outstd_logic）;
endentityneimacs0;
architecturenm0ofneimacs0is
componentmux8_0
port（D7,D6,D5,D4,D3,D2,D1,D0,D,C,B:
instd_logic;
y:
outstd_logic）;
endcomponent;
componenttri_gate0
port（din0,en:
instd_logic;
dout0:
outstd_logic）;
endcomponent;
signalIO:
std_logic;
begin
u1:
mux8_0
portmap（in0_8,in0_7,in0_6,in0_5,in0_4,in0_3,in0_2,in0_1,K3,K2,K1,IO）;
u2:
tri_gate0
portmap（din0=>IO,en=>sx0,dout0=>out0）;
endarchitecturenm0;
libraryieee;
useieee.std_logic_1164.all;
entitymux8_0is
port（D7,D6,D5,D4,D3,D2,D1,D0:
instd_logic;
D,C,B:
instd_logic;
y:
outstd_logic）;
endmux8_0;
architecturertlofmux8_0is
signalsel:
std_logic_vector（2downto0）;
begin
;
withselselect
y<=D0when"000",
D1when"001",
D2when"010",
D3when"011",
D4when"100",
D5when"101",
D6when"110",
D7when"111",
'0'whenothers;
endrtl;
libraryieee;
useieee.std_logic_1164.all;
entitytri_gate0is
port（din0,en:
instd_logic;
dout0:
outstd_logic）;
endtri_gate0;
architecturezasoftri_gate0is
begin
dout0<=din0whenen='1'else
'1';
endzas;
3．时序信号产生器
libraryieee;
useieee.std_logic_1164.all;
entityshixusuccessfulis
port（B:
instd_logic;
S3,S2,S1,S0:
outstd_logic）;
endentityshixusuccessful;
architecturesx1ofshixusuccessfulis
componentcount32
port（X1:
instd_logic;
E,D,C,B,A:
outstd_logic）;
endcomponent;
componentyimaqi
port（F2,F1:
instd_logic;
Y3,Y2,Y1,Y0:
outstd_logic）;
endcomponent;
componentnand0_1
port（X2:
instd_logic;
out2:
outstd_logic）;
endcomponent;
signalin1,in2,in3,in4,in5,in6,in7:
std_logic;
begin
u1:
nand0_1portmap（X2=>B,out2=>in1）;
u2:
count32
portmap（X1=>in1,D=>in2,E=>in3）;
u3:
yimaqi
portmap（F1=>in2,F2=>in3,Y0=>in4,Y1=>in5,Y2=>in6,Y3=>in7）;
u4:
nand0_1portmap（X2=>in4,out2=>S0）;
u5:
nand0_1portmap（X2=>in5,out2=>S1）;
u6:
nand0_1portmap（X2=>in6,out2=>S2）;
u7:
nand0_1portmap（X2=>in7,out2=>S3）;
endarchitecturesx1;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycount32is
port（X1:
instd_logic;
E,D,C,B,A:
outstd_logic）;
endcount32;
architecturertlofcount32is
signalcount_5:
std_logic_vector（4downto0）;
begin
process（X1）
begin
if（X1'eventandX1='1'）then
if（count_5="11111"）then
count_5<="00000";
else
count_5<=count_5+1;
endif;
endif;
endprocess;
A<=count_5（0）;
B<=count_5
（1）;
C<=count_5
（2）;
D<=count_5（3）;
E<=count_5（4）;
endrtl;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyimaqiis
port（F2,F1:
instd_logic;
Y3,Y2,Y1,Y0:
outstd_logic）;
endyimaqi;
architecturertlofyimaqiis
signalindata:
std_logic_vector（1downto0）;
signalY:
std_logic_vector（3downto0）;
begin
indata<=F2&F1;
process（indata）
begin
caseindatais
when"00"=>Y<="1110";
when"01"=>Y<="1101";
when"10"=>Y<="1011";
when"11"=>Y<="0111";
whenothers=>Y<="XXXX";
endcase;
endprocess;
Y3<=Y（3）;
Y2<=Y
（2）;
Y1<=Y
（1）;
Y0<=Y（0）;
endrtl;
libraryieee;
useieee.std_logic_1164.all;
entitynand0_1is
port（X2:
instd_logic;
out2:
outstd_logic）;
endnand0_1;
architecturenand_0ofnand0_1is
begin
out2<=notX2;
endnand_0;
4．基带发信系统程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfujieqiallis
port（clk,ena,a0,a1,a2,a3,a4,a5,a6,a7,
b0,b1,b2,b3,b4,b5,b6,b7,
c0,c1,c2,c3,c4,c5,c6,c7,
d0,d1,d2,d3,d4,d5,d6,d7:
instd_logic;
s0,s1,s2,s3,fujiout:
outstd_logic）;
endfujieqiall;
architectureffoffujieqiallis
componentcount16
port（clk:
instd_logic;
D,C,B,A:
outstd_logic）;
endcomponent;
componentneimacs0
port（in0_8,in0_7,in0_6,in0_5,in0_4,in0_3,in0_2,in0_1,
K3,K2,K1,sx0:
instd_logic;
out0:
outstd_logic）;
endcomponent;
componentshixusuccessful
port（B:
instd_logic;
S3,S2,S1,S0:
outstd_logic）;
endcomponent;
componentmen
port（in1:
instd_logic;
out1:
outstd_logic）;
endcomponent;
componentandmen
port（in1,in2,in3,in4:
instd_logic;
outp:
outstd_logic）;
endcomponent;
componentdjhlatch
port（D,ena:
instd_logic;
q1:
outstd_logic）;
endcomponent;
signalw1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,
w12,w13,w14,w15,w16:
std_logic;
begin
m1:
neimacs0
portmap（in0_1=>a0,in0_2=>a1,in0_3=>a2,in0_4=>a3,in0_5=>a4,in0_6=>a5,
in0_7=>a6,in0_8=>a7,K3=>w3,K2=>w2,K1=>w1,sx0=>w4,out0=>w15）;
m2:
neimacs0
portmap（in0_1=>b0,in0_2=>b1,in0_3=>b2,in0_4=>b3,in0_5=>b4,in0_6=>b5,
in0_7=>b6,in0_8=>b7,K3=>w3,K2=>w2,K1=>w1,sx0=>w5,out0=>w14）;
m3:
neimacs0
portmap（in0_1=>c0,in0_2=>c1,in0_3=>c2,in0_4=>c3,in0_5=>c4,in0_6=>c5,
in0_7=>c6,in0_8=>c7,K3=>w3,K2=>w2,K1=>w1,sx0=>w6,out0=>w13）;
m4:
neimacs0
portmap（in0_1=>d0,in0_2=>d1,in0_3=>d2,in0_4=>d3,in0_5=>d4,in0_6=>d5,
in0_7=>d6,in0_8=>d7,K3=>w3,K2=>w2,K1=>w1,sx0=>w7,out0=>w12）;
m5:
shixusuccessfulportmap（b=>clk,S3=>w7,S2=>w6,S1=>w5,S0=>w4）;
m6:
count16portmap（clk=>clk,D=>W1,C=>W2,B=>W3）;
m7:
menportmap（in1=>w7,out1=>s3）;
m8:
menportmap（in1=>w6,out1=>s2）;
m9:
menportmap（in1=>w5,out1=>s1）;
m10:
menportmap（in1=>w4,out1=>s0）;
m11:
andmenportmap（in1=>w12,in2=>w13,in3=>w14,in4=>w15,outp=>w16）;
m12:
djhlatchportmap（D=>w16,ena=>ena,q1=>fujiout）;
endff;
libraryieee;
useieee.std_logic_1164.all;
entitymenis
port（in1:
instd_logic;
out1:
outstd_logic）;
endmen;
architectureoneofmenis
begin
out1<=in1;
endone;
libraryieee;
useieee.std_logic_1164.all;
entityandmenis
port（in1,in2,in3,in4:
instd_logic;
outp:
outstd_logic）;
endandmen;
architectureoneofandmenis
begin
outp<=in1andin2andin3andin4;
endone;
libraryieee;
useieee.std_logic_1164.all;
entitydjhlatchis
port（d,ena:
instd_logic;
q1:
outstd_logic）;
endentitydjhlatch;
architectureoneofdjhlatchis
signalsig_save:
std_logic;
begin
process（d,ena）
begin
ifena='1'then
sig_save<=d;
endif;
q1<=sig_save;
endprocess;
endarchitectureone;
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