多路信号复用的基带发信系统.docx

1、多路信号复用的基带发信系统1. 分频器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count16 is port(clk:in std_logic; D,C,B,A:out std_logic);end count16;architecture rtl of count16 is signal count_4:std_logic_vector(3 downto 0); begin process(clk) begin if(clkevent and clk=1) then if(

2、count_4=1111) then count_4=0000; else count_4IO,en=sx0,dout0=out0);end architecture nm0;library ieee;use ieee.std_logic_1164.all;entity mux8_0 is port(D7,D6,D5,D4,D3,D2,D1,D0:in std_logic; D,C,B:in std_logic; y:out std_logic);end mux8_0;architecture rtl of mux8_0 is signal sel:std_logic_vector(2 dow

3、nto 0);begin ; with sel selecty=D0 when 000, D1 when 001, D2 when 010, D3 when 011, D4 when 100, D5 when 101, D6 when 110, D7 when 111, 0 when others;end rtl;library ieee;use ieee.std_logic_1164.all;entity tri_gate0 is port(din0,en:in std_logic; dout0:out std_logic);end tri_gate0;architecture zas of

4、 tri_gate0 isbegin dout0B,out2=in1); u2:count32 port map(X1=in1,D=in2,E=in3); u3:yimaqi port map (F1=in2, F2=in3, Y0=in4, Y1=in5, Y2=in6, Y3=in7); u4:nand0_1 port map(X2=in4,out2=S0); u5:nand0_1 port map(X2=in5,out2=S1); u6:nand0_1 port map(X2=in6,out2=S2); u7:nand0_1 port map(X2=in7,out2=S3);end ar

5、chitecture sx1;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count32 is port(X1:in std_logic; E,D,C,B,A:out std_logic);end count32;architecture rtl of count32 is signal count_5:std_logic_vector(4 downto 0); begin process(X1) begin if(X1event and X1=1) then if(count_

6、5=11111) then count_5=00000; else count_5=count_5+1; end if; end if; end process;A=count_5(0);B=count_5(1);C=count_5(2);D=count_5(3);E=count_5(4);end rtl;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yimaqi is port(F2,F1:in std_logic; Y3,Y2,Y1,Y0:out std_logic);end

7、yimaqi;architecture rtl of yimaqi is signal indata:std_logic_vector(1 downto 0); signal Y:std_logic_vector(3 downto 0);begin indataYYYYY=XXXX; end case; end process;Y3=Y(3);Y2=Y(2);Y1=Y(1);Y0=Y(0);end rtl;library ieee;use ieee.std_logic_1164.all;entity nand0_1 is port(X2:in std_logic; out2:out std_l

8、ogic);end nand0_1;architecture nand_0 of nand0_1 isbegin out2a0,in0_2=a1,in0_3=a2,in0_4=a3,in0_5=a4,in0_6=a5, in0_7=a6,in0_8=a7,K3=w3,K2=w2,K1=w1,sx0=w4,out0=w15);m2:neimacs0 port map(in0_1=b0,in0_2=b1,in0_3=b2,in0_4=b3,in0_5=b4,in0_6=b5, in0_7=b6,in0_8=b7,K3=w3,K2=w2,K1=w1,sx0=w5,out0=w14);m3:neima

9、cs0 port map(in0_1=c0,in0_2=c1,in0_3=c2,in0_4=c3,in0_5=c4,in0_6=c5, in0_7=c6,in0_8=c7,K3=w3,K2=w2,K1=w1,sx0=w6,out0=w13);m4:neimacs0 port map(in0_1=d0,in0_2=d1,in0_3=d2,in0_4=d3,in0_5=d4,in0_6=d5, in0_7=d6,in0_8=d7,K3=w3,K2=w2,K1=w1,sx0=w7,out0=w12);m5:shixusuccessful port map(b=clk,S3=w7,S2=w6,S1=w

10、5,S0=w4);m6:count16 port map(clk=clk,D=W1,C=W2,B=W3);m7:men port map(in1=w7,out1=s3);m8:men port map(in1=w6,out1=s2);m9:men port map(in1=w5,out1=s1);m10:men port map(in1=w4,out1=s0);m11:andmen port map(in1=w12,in2=w13,in3=w14,in4=w15,outp=w16);m12:djhlatch port map(D=w16,ena=ena,q1=fujiout);end ff;l

11、ibrary ieee;use ieee.std_logic_1164.all;entity men is port(in1:in std_logic; out1:out std_logic);end men;architecture one of men is begin out1=in1;end one;library ieee;use ieee.std_logic_1164.all;entity andmen is port(in1,in2,in3,in4:in std_logic; outp:out std_logic);end andmen;architecture one of a

12、ndmen is begin outp=in1 and in2 and in3 and in4;end one;library ieee;use ieee.std_logic_1164.all;entity djhlatch isport(d,ena:in std_logic; q1:out std_logic);end entity djhlatch;architecture one of djhlatch issignal sig_save:std_logic;begin process(d,ena)beginif ena=1 then sig_save=d;end if; q1=sig_save;end process;end architecture one;仿真