心率测试仪.docx
《心率测试仪.docx》由会员分享，可在线阅读，更多相关《心率测试仪.docx（17页珍藏版）》请在冰豆网上搜索。
心率测试仪
1.消抖电路：
2.分频器：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfpqis
port（clk:
instd_logic;
f50k:
bufferstd_logic:
='0';
f1k:
bufferstd_logic;
f5k:
bufferstd_logic;
f2k:
bufferstd_logic;
f100hz:
bufferstd_logic;
f2hz:
bufferstd_logic;
f1s:
bufferstd_logic;
f6s:
bufferstd_logic:
='1'）;
endfpq;
architectureoneoffpqis
signalcount_6s,count_100:
std_logic_vector（3downto0）;
signalcount_1m,count_1s,count_05s,count_1k,count_2k,
count_5k:
std_logic_vector（8downto0）;
signalcount_hec:
std_logic_vector（9downto0）;
signalfpq_hec:
std_logic_vector（9downto0）;
Begin
--50khz
process（clk）
begin
if（clk'eventandclk='1'）then
if（count_1m="011111001"）then--500分频（系统时钟25MHz）
count_1m<="000000000";
f50k<=notf50k;
else
count_1m<=count_1m+1;
endif;
endif;
endprocess;
--5Khz
process（f50k）
begin
if（f50k'eventandf50k='1'）then
if（count_5k="00000100"）then--10分频
count_5k<="000000000";
f5k<=notf5k;
else
count_5k<=count_5k+1;
endif;
endif;
endprocess;
--1khz
process（f50k）
begin
if（f50k'eventandf50k='1'）then
if（count_1k="00011000"）then--50分频
count_1k<="000000000";
f1k<=notf1k;
else
count_1k<=count_1k+1;
endif;
endif;
endprocess;
--2.5khz
process（f50k）
begin
if（f50k'eventandf50k='1'）then
if（count_2k="00001001"）then--20分频
count_2k<="000000000";
f2k<=notf2k;
else
count_2k<=count_2k+1;
endif;
endif;
endprocess;
--100hz
process（f1k）
begin
if（f1k'eventandf1k='1'）then
if（count_100="0100"）then--10分频
count_100<="0000";
f100hz<=notf100hz;
else
count_100<=count_100+1;
endif;
endif;
endprocess;
--2hz
process（f1k）
begin
if（f1k'eventandf1k='1'）then
if（count_05s="011111001"）then--500分频
count_05s<="000000000";
f2hz<=notf2hz;
else
count_05s<=count_05s+1;
endif;
endif;
endprocess;
--1hz
process（f1k）
begin
if（f1k'eventandf1k='1'）then
if（count_1s="111110100"）then--1000分频
count_1s<="000000000";
f1s<=notf1s;
else
count_1s<=count_1s+1;
endif;
endif;
endprocess;
--6s
process（f1s）
begin
if（f1s'eventandf1s='1'）then
if（count_6s="0101"）then
f6s<='0';
count_6s<=count_6s+1;
elsif（count_6s="0110"）then
f6s<='1';
count_6s<="0000";
else
count_6s<=count_6s+1;
f6s<='1';
endif;
endif;
endprocess;
endone;
3.计数器：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityjsqis
Port（
jsq_clk,jsq_clr:
instd_logic;
jsq_h_loc:
bufferstd_logic_vector（3downto0）;--高位
jsq_l_loc:
bufferstd_logic_vector（3downto0）;--低位
jsq_situ:
bufferstd_logic_vector（1downto0））;--状态
endjsq;
architectureoneofjsqis
signaljsq_h,jsq_l:
std_logic_vector（3downto0）;
signaljsqet_h,jsqet_l:
std_logic_vector（3downto0）;
begin
process（jsq_clk,jsq_clr）
begin
if（jsq_clr='0'）then--计数,同步复位
jsq_h<="0000";jsq_l<="0000";
elsif（jsq_clk'eventandjsq_clk='1'）then
if（jsq_l="0000"andjsq_h="0010"）then
jsq_l<="0000";jsq_h<="0010";
elsif（jsq_l="1001"andjsq_h<"0010"）then
jsq_l<="0000";
jsq_h<=jsq_h+1;
else
jsq_l<=jsq_l+1;
endif;
endif;
--比较状态
if（jsq_h_loc>"0001"）then--心率过速
jsq_situ<="11";
elsif（jsq_h_loc="0000"andjsq_l_loc<"0110"）then--心率过缓
jsq_situ<="01";
elsif（jsq_h_loc="0000"andjsq_l_loc="0000"）then--心跳停止
jsq_situ<="00";
else
jsq_situ<="10";--正常心率
endif;
endprocess;
process（jsq_clr,jsq_l,jsq_h）
begin
if（jsq_clr'eventandjsq_clr='0'）then
jsq_h_loc<=jsq_h;
jsq_l_loc<=jsq_l;
endif;
endprocess;
endone;
4.蜂鸣器：
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityfmqis
Port（
fmq_situ:
instd_logic_vector（1downto0）;
fmq_1k,fmq_05s,fmq_2k,fmq_5k,fmq_100,fmq_heart:
instd_logic;
fmq_show,fmq_bee:
bufferstd_logic）;
endfmq;
architectureoneoffmqis
begin
process（fmq_1k,fmq_2k,fmq_5k,fmq_show,fmq_bee）
begin
if（fmq_situ="00"）then--心跳停止，连续报警，闪动显示
if（fmq_100='1'andfmq_heart='0'）then
fmq_bee<='0';
else
fmq_bee<='1';
endif;
if（fmq_05s='1'）then
fmq_show<='0';
else
fmq_show<='1';
endif;
elsif（fmq_situ="10"）then
if（fmq_heart='1'andfmq_2k='1'）then--正常心率，非闪动显示，同步声响
fmq_bee<='0';
else
fmq_bee<='1';
endif;
fmq_show<='0';
elsif（fmq_situ="01"）then
if（fmq_05s='1'andfmq_1k='1'）then--心率过缓，闪动显示，间隔报警
fmq_bee<='0';
else
fmq_bee<='1';
endif;
if（fmq_05s='1'）then
fmq_show<='0';
elsefmq_show<='1';
endif;
elsif（fmq_situ="11"）then
if（fmq_05s='1'andfmq_5k='1'）then--心率过速，闪动显示，间隔报警
fmq_bee<='0';
else
fmq_bee<='1';
endif;
if（fmq_05s='1'）then
fmq_show<='0';
else
fmq_show<='1';
endif;
endif;
endprocess;
endone;
5.寄存器：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityjcqis
Port（
h:
instd_logic_vector（3downto0）;
l:
instd_logic_vector（3downto0）;
jcq_situ:
instd_logic_vector（1downto0）;
jcq_clk:
instd_logic;
el:
bufferstd_logic_vector（3downto0）;
eh:
bufferstd_logic_vector（3downto0）;
th:
bufferstd_logic_vector（3downto0）;
tl:
bufferstd_logic_vector（3downto0））;
endjcq;
architectureoneofjcqis
signalhertet_h,hertet_l:
std_logic_vector（3downto0）;
begin
process（jcq_situ,h,l,el,eh）
begin
if（jcq_clk'eventandjcq_clk='1'）then
if（jcq_situ/="10"）then--不正常心率
eh<=h;
el<=l;
hertet_l<="0110";
hertet_h<="0000";
endif;
endif;
endprocess;
process（jcq_clk,hertet_l,hertet_h）--不正常心率时间
begin
if（jcq_clk'eventandjcq_clk='1'）then
th<=hertet_h;tl<=hertet_l;
endif;
endprocess;
endone;
6.查询器：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycxqis
Port（nowh,nowl,eh,el,th,tl:
instd_logic_vector（3downto0）;
oh,om,ol:
outstd_logic_vector（3downto0）;
chaxun,clk:
instd_logic）;
endcxq;
architectureoneofcxqis
signaldisply:
std_logic_vector（1downto0）;
signalcount:
std_logic_vector（3downto0）:
="1000";
signalflg:
std_logic;
begin
process（chaxun,clk）
begin
if（chaxun='0'）then
count<="0000";
elsif（clk'eventandclk='1'）then
if（count="1111"）then
count<=count;
else
count<=count+1;
endif;
endif;
endprocess;
process（nowh,nowl,eh,el,th,tl,disply）
begin
if（count>"0110"）then--6s之后恢复检测功能
oh<=nowh;
om<=nowl;
ol<="0000";
elsif（count<"0011"）then--显示不正常心率3s
oh<=eh;
om<=el;
ol<="0000";
else--显示不正常心率时间3s
oh<="0000";
om<=th;
ol<=tl;
endif;
endprocess;
endone;
7.显示器：
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityxsqis
PORT（
clk,flag,show:
INstd_logic;
high_bit:
instd_logic_vector（3downto0）;
middle_bit:
instd_logic_vector（3downto0）;
low_bit:
instd_logic_vector（3downto0）;
en:
outstd_logic_vector（2DOWNTO0）;
dataout:
outstd_logic_vector（7DOWNTO0）
）;
endxsq;
architecturearchofxsqis
signaldataout8:
std_logic_vector（7downto0）;
signalen3:
std_logic_vector（2downto0）:
="001";
signaldata4:
std_logic_vector（3downto0）;
begin
dataout<=dataout8;
en<=en3;
process（clk）
begin
if（show='1'）then
en3<="000";
elsif（flag='1'andflag'event）then--片（段）选
if（en3="001"）then
en3<="010";
elsif（en3="010"）then
en3<="100";
elsif（en3="100"）then
en3<="001";
elsif（en3="000"）then
en3<="001";
endif;
endif;
endprocess;
process（clk）
begin
if（clk='1'andclk'event）then--位选（数码管）
if（en3="100"）then
data4<=low_bit;
elsif（en3="010"）then
data4<=middle_bit;
elsif（en3="001"）then
data4<=high_bit;
endif;
endif;
endprocess;
process（data4）
begin
casedata4is
WHEN"0000"=>
dataout8<="00000011";
WHEN"0001"=>
dataout8<="10011111";
WHEN"0010"=>
dataout8<="00100101";
WHEN"0011"=>
dataout8<="00001101";
WHEN"0100"=>
dataout8<="10011001";
WHEN"0101"=>
dataout8<="01001001";
WHEN"0110"=>
dataout8<="11000001";
WHEN"0111"=>
dataout8<="00011111";
WHEN"1000"=>
dataout8<="00000001";
WHEN"1001"=>
dataout8<="00011001";
WHEN"1010"=>
dataout8<="00100000";
WHEN"1011"=>
dataout8<="01100010";
WHEN"1100"=>
dataout8<="10000010";
WHEN"1101"=>
dataout8<="10000010";
WHEN"1110"=>
dataout8<="00100001";
WHEN"1111"=>
dataout8<="01110000";
WHENOTHERS=>
dataout8<="11111111";
ENDCASE;
ENDPROCESS;
endarch;
升级会员 